| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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|
//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// SIEReceiver
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
|
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//// restriction provided that this copyright statement is not ////
|
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//// removed from the file and that any derivative work contains ////
|
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
|
//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\siereceiver.v
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// $Id: siereceiver.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
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// Generated : 09/06/04 06:18:21
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// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\siereceiver.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
|
//
|
//
|
// Description :
|
// $Log: not supported by cvs2svn $
|
//
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//
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//-------------------------------------------------------------------------------------------------
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|
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`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
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|
|
|
module SIEReceiver (RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut, clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst);
|
module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);
|
input [1:0] RxWireDataIn;
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|
input RxWireDataWEn;
|
|
input clk;
|
input clk;
|
input processRxBitRdyIn;
|
input processRxBitRdyIn;
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input rst;
|
input rst;
|
output [1:0] RxBitsOut;
|
input [1:0]RxWireDataIn;
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output SIERxRdyOut;
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input RxWireDataWEn;
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output [1:0] connectState;
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output [1:0] connectState;
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output processRxBitsWEn;
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output processRxBitsWEn;
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output [1:0]RxBitsOut;
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output SIERxRdyOut;
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reg [1:0] RxBitsOut, next_RxBitsOut;
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wire [1:0] RxWireDataIn;
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wire RxWireDataWEn;
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reg SIERxRdyOut, next_SIERxRdyOut;
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wire clk;
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wire clk;
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reg [1:0] connectState, next_connectState;
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reg [1:0] connectState, next_connectState;
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wire processRxBitRdyIn;
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wire processRxBitRdyIn;
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reg processRxBitsWEn, next_processRxBitsWEn;
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reg processRxBitsWEn, next_processRxBitsWEn;
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wire rst;
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wire rst;
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reg [1:0]RxBitsOut, next_RxBitsOut;
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wire [1:0]RxWireDataIn;
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wire RxWireDataWEn;
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reg SIERxRdyOut, next_SIERxRdyOut;
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|
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// diagram signals declarations
|
// diagram signals declarations
|
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reg [1:0]RxBits, next_RxBits;
|
reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
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reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
|
reg [7:0]RXWaitCount, next_RXWaitCount;
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reg [7:0]RXWaitCount, next_RXWaitCount;
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reg [1:0]RxBits, next_RxBits;
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|
|
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// BINARY ENCODED state machine: rcvr
|
// BINARY ENCODED state machine: rcvr
|
// State codes definitions:
|
// State codes definitions:
|
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
|
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
|
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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| Line 62... |
Line 92... |
`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
|
`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
|
`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
|
`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
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`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
|
`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
|
`define FS_CONN_PROC_RX_BITS1 4'b1100
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`define FS_CONN_PROC_RX_BITS1 4'b1100
|
|
|
reg [3:0] CurrState_rcvr;
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reg [3:0]CurrState_rcvr, NextState_rcvr;
|
reg [3:0] NextState_rcvr;
|
|
|
|
|
|
//--------------------------------------------------------------------
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|
// Machine: rcvr
|
// Machine: rcvr
|
//--------------------------------------------------------------------
|
|
//----------------------------------
|
|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)
|
always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or processRxBitRdyIn or SIERxRdyOut or connectState or RxBitsOut or processRxBitsWEn or CurrState_rcvr)
|
begin
|
begin : rcvr_NextState
|
|
NextState_rcvr <= CurrState_rcvr;
|
NextState_rcvr <= CurrState_rcvr;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_RxBits <= RxBits;
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next_SIERxRdyOut <= SIERxRdyOut;
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next_RXStMachCurrState <= RXStMachCurrState;
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next_RXWaitCount <= RXWaitCount;
|
next_RXWaitCount <= RXWaitCount;
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next_connectState <= connectState;
|
next_connectState <= connectState;
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next_RxBitsOut <= RxBitsOut;
|
next_RXStMachCurrState <= RXStMachCurrState;
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next_processRxBitsWEn <= processRxBitsWEn;
|
next_processRxBitsWEn <= processRxBitsWEn;
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|
next_RxBitsOut <= RxBitsOut;
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|
next_RxBits <= RxBits;
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next_SIERxRdyOut <= SIERxRdyOut;
|
case (CurrState_rcvr) // synopsys parallel_case full_case
|
case (CurrState_rcvr) // synopsys parallel_case full_case
|
`WAIT_BIT:
|
`WAIT_BIT:
|
if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
|
|
begin
|
begin
|
NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
|
if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
|
|
begin
|
|
NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
|
begin
|
begin
|
NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
|
NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
|
begin
|
begin
|
NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
|
NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
|
begin
|
begin
|
NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
|
NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
|
begin
|
begin
|
NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
|
NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
|
begin
|
begin
|
NextState_rcvr <= `DISCNCT_CHK_RXBITS;
|
NextState_rcvr <= `DISCNCT_CHK_RXBITS;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
|
else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
|
begin
|
begin
|
NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
|
NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
|
next_RxBits <= RxWireDataIn;
|
next_RxBits <= RxWireDataIn;
|
next_SIERxRdyOut <= 1'b0;
|
next_SIERxRdyOut <= 1'b0;
|
end
|
end
|
|
end
|
`START_SRX:
|
`START_SRX:
|
begin
|
begin
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_RXWaitCount <= 8'h00;
|
next_RXWaitCount <= 8'h00;
|
next_connectState <= `DISCONNECT;
|
next_connectState <= `DISCONNECT;
|
| Line 139... |
Line 167... |
next_processRxBitsWEn <= 1'b0;
|
next_processRxBitsWEn <= 1'b0;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
end
|
end
|
`DISCNCT_CHK_RXBITS:
|
`DISCNCT_CHK_RXBITS:
|
|
begin
|
if (RxBits == `ZERO_ONE)
|
if (RxBits == `ZERO_ONE)
|
begin
|
begin
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
|
next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
|
next_RXWaitCount <= 8'h00;
|
next_RXWaitCount <= 8'h00;
|
| Line 158... |
Line 187... |
else
|
else
|
begin
|
begin
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
|
end
|
`WAIT_FS_CONN_CHK_RX_BITS:
|
`WAIT_FS_CONN_CHK_RX_BITS:
|
begin
|
begin
|
if (RxBits == `ONE_ZERO)
|
if (RxBits == `ONE_ZERO)
|
begin
|
begin
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
| Line 171... |
Line 201... |
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
|
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_RXStMachCurrState = `DISCONNECT_ST;
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
end
|
end
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
`WAIT_LS_CONN_CHK_RX_BITS:
|
`WAIT_LS_CONN_CHK_RX_BITS:
|
| Line 189... |
Line 219... |
next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
|
next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_RXStMachCurrState = `DISCONNECT_ST;
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
end
|
end
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
`LS_CONN_CHK_RX_BITS:
|
`LS_CONN_CHK_RX_BITS:
|
|
begin
|
if (processRxBitRdyIn == 1'b1)
|
if (processRxBitRdyIn == 1'b1)
|
begin
|
begin
|
NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
|
NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
begin
|
begin
|
| Line 206... |
Line 237... |
next_RXWaitCount <= 0;
|
next_RXWaitCount <= 0;
|
end
|
end
|
next_processRxBitsWEn <= 1'b1;
|
next_processRxBitsWEn <= 1'b1;
|
next_RxBitsOut <= RxBits;
|
next_RxBitsOut <= RxBits;
|
end
|
end
|
|
end
|
`LS_CONN_PROC_RX_BITS:
|
`LS_CONN_PROC_RX_BITS:
|
begin
|
begin
|
next_processRxBitsWEn <= 1'b0;
|
next_processRxBitsWEn <= 1'b0;
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
`FS_CONN_CHK_RX_BITS1:
|
`FS_CONN_CHK_RX_BITS1:
|
|
begin
|
if (processRxBitRdyIn == 1'b1)
|
if (processRxBitRdyIn == 1'b1)
|
begin
|
begin
|
NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
|
NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
begin
|
begin
|
| Line 226... |
Line 259... |
next_processRxBitsWEn <= 1'b1;
|
next_processRxBitsWEn <= 1'b1;
|
next_RxBitsOut <= RxBits;
|
next_RxBitsOut <= RxBits;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
//early indication of ready
|
//early indication of ready
|
end
|
end
|
|
end
|
`FS_CONN_PROC_RX_BITS1:
|
`FS_CONN_PROC_RX_BITS1:
|
begin
|
begin
|
next_processRxBitsWEn <= 1'b0;
|
next_processRxBitsWEn <= 1'b0;
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
`WAIT_LS_DIS_CHK_RX_BITS:
|
`WAIT_LS_DIS_CHK_RX_BITS:
|
|
begin
|
if (processRxBitRdyIn == 1'b1)
|
if (processRxBitRdyIn == 1'b1)
|
begin
|
begin
|
NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
|
NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
begin
|
begin
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
begin
|
begin
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_connectState = `DISCONNECT;
|
next_connectState <= `DISCONNECT;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_RXStMachCurrState = `CONNECT_LOW_SPEED_ST;
|
next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
|
end
|
end
|
next_processRxBitsWEn <= 1'b1;
|
next_processRxBitsWEn <= 1'b1;
|
end
|
end
|
|
end
|
`WAIT_LS_DIS_PROC_RX_BITS:
|
`WAIT_LS_DIS_PROC_RX_BITS:
|
begin
|
begin
|
next_processRxBitsWEn <= 1'b0;
|
next_processRxBitsWEn <= 1'b0;
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
| Line 264... |
Line 300... |
next_processRxBitsWEn <= 1'b0;
|
next_processRxBitsWEn <= 1'b0;
|
NextState_rcvr <= `WAIT_BIT;
|
NextState_rcvr <= `WAIT_BIT;
|
next_SIERxRdyOut <= 1'b1;
|
next_SIERxRdyOut <= 1'b1;
|
end
|
end
|
`WAIT_FS_DIS_CHK_RX_BITS2:
|
`WAIT_FS_DIS_CHK_RX_BITS2:
|
|
begin
|
if (processRxBitRdyIn == 1'b1)
|
if (processRxBitRdyIn == 1'b1)
|
begin
|
begin
|
NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
|
NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
begin
|
begin
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
begin
|
begin
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_RXStMachCurrState <= `DISCONNECT_ST;
|
next_connectState = `DISCONNECT;
|
next_connectState <= `DISCONNECT;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_RXStMachCurrState = `CONNECT_FULL_SPEED_ST;
|
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
|
end
|
end
|
next_processRxBitsWEn <= 1'b1;
|
next_processRxBitsWEn <= 1'b1;
|
end
|
end
|
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : rcvr_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_rcvr <= `START_SRX;
|
CurrState_rcvr <= `START_SRX;
|
else
|
else
|
CurrState_rcvr <= NextState_rcvr;
|
CurrState_rcvr <= NextState_rcvr;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : rcvr_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXStMachCurrState <= `DISCONNECT_ST;
|
|
RXWaitCount <= 8'h00;
|
|
RxBits <= 2'b00;
|
|
connectState <= `DISCONNECT;
|
connectState <= `DISCONNECT;
|
RxBitsOut <= 2'b00;
|
|
processRxBitsWEn <= 1'b0;
|
processRxBitsWEn <= 1'b0;
|
|
RxBitsOut <= 2'b00;
|
SIERxRdyOut <= 1'b1;
|
SIERxRdyOut <= 1'b1;
|
|
RXWaitCount <= 8'h00;
|
|
RXStMachCurrState <= `DISCONNECT_ST;
|
|
RxBits <= 2'b00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXStMachCurrState <= next_RXStMachCurrState;
|
|
RXWaitCount <= next_RXWaitCount;
|
|
RxBits <= next_RxBits;
|
|
connectState <= next_connectState;
|
connectState <= next_connectState;
|
RxBitsOut <= next_RxBitsOut;
|
|
processRxBitsWEn <= next_processRxBitsWEn;
|
processRxBitsWEn <= next_processRxBitsWEn;
|
|
RxBitsOut <= next_RxBitsOut;
|
SIERxRdyOut <= next_SIERxRdyOut;
|
SIERxRdyOut <= next_SIERxRdyOut;
|
|
RXWaitCount <= next_RXWaitCount;
|
|
RXStMachCurrState <= next_RXStMachCurrState;
|
|
RxBits <= next_RxBits;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
