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[/] [usbhostslave/] [tags/] [rel_01_01/] [RTL/] [serialInterfaceEngine/] [usbTxWireArbiter.v] - Diff between revs 9 and 14

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Rev 9 Rev 14
Line 46... Line 46... 
`include "usbConstants_h.v"
 
`include "usbConstants_h.v"
 
`include "usbSerialInterfaceEngine_h.v"
 
`include "usbSerialInterfaceEngine_h.v"
 
 
 
 
 
 
 
 
 
 
 
 
 
module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
 
module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
 
input   clk;
 
input   clk;
 
input   prcTxByteCtrl;
 
input   prcTxByteCtrl;
 
input   [1:0]prcTxByteData;
 
input   [1:0]prcTxByteData;
 
 
 
input   prcTxByteFSRate;
 
input   prcTxByteReq;
 
input   prcTxByteReq;
 
input   prcTxByteWEn;
 
input   prcTxByteWEn;
 
input   rst;
 
input   rst;
 
input   SIETxCtrl;
 
input   SIETxCtrl;
 
input   [1:0]SIETxData;
 
input   [1:0]SIETxData;
 
 
 
input   SIETxFSRate;
 
input   SIETxReq;
 
input   SIETxReq;
 
input   SIETxWEn;
 
input   SIETxWEn;
 
input   USBWireRdyIn;
 
input   USBWireRdyIn;
 
output  prcTxByteGnt;
 
output  prcTxByteGnt;
 
output  SIETxGnt;
 
output  SIETxGnt;
 
output  [1:0]TxBits;
 
output  [1:0]TxBits;
 
output  TxCtl;
 
output  TxCtl;
 
 
 
output  TxFSRate;
 
output  USBWireRdyOut;
 
output  USBWireRdyOut;
 
output  USBWireWEn;
 
output  USBWireWEn;
 
 
 
 
 
wire    clk;
 
wire    clk;
 
wire    prcTxByteCtrl;
 
wire    prcTxByteCtrl;
 
wire    [1:0]prcTxByteData;
 
wire    [1:0]prcTxByteData;
 
 
 
wire    prcTxByteFSRate;
 
reg     prcTxByteGnt, next_prcTxByteGnt;
 
reg     prcTxByteGnt, next_prcTxByteGnt;
 
wire    prcTxByteReq;
 
wire    prcTxByteReq;
 
wire    prcTxByteWEn;
 
wire    prcTxByteWEn;
 
wire    rst;
 
wire    rst;
 
wire    SIETxCtrl;
 
wire    SIETxCtrl;
 
wire    [1:0]SIETxData;
 
wire    [1:0]SIETxData;
 
 
 
wire    SIETxFSRate;
 
reg     SIETxGnt, next_SIETxGnt;
 
reg     SIETxGnt, next_SIETxGnt;
 
wire    SIETxReq;
 
wire    SIETxReq;
 
wire    SIETxWEn;
 
wire    SIETxWEn;
 
reg     [1:0]TxBits, next_TxBits;
 
reg     [1:0]TxBits, next_TxBits;
 
reg     TxCtl, next_TxCtl;
 
reg     TxCtl, next_TxCtl;
 
 
 
reg     TxFSRate, next_TxFSRate;
 
wire    USBWireRdyIn;
 
wire    USBWireRdyIn;
 
reg     USBWireRdyOut, next_USBWireRdyOut;
 
reg     USBWireRdyOut, next_USBWireRdyOut;
 
reg     USBWireWEn, next_USBWireWEn;
 
reg     USBWireWEn, next_USBWireWEn;
 
 
 
 
 
// diagram signals declarations
 
// diagram signals declarations
Line 102... Line 108... 
always @(USBWireRdyIn)
 
always @(USBWireRdyIn)
 
begin
 
begin
 
USBWireRdyOut <= USBWireRdyIn;
 
USBWireRdyOut <= USBWireRdyIn;
 
end
 
end
 
always @(muxSIENotPTXB or SIETxWEn or SIETxData or
 
always @(muxSIENotPTXB or SIETxWEn or SIETxData or
 
SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
 
SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
 
 
 
SIETxFSRate or prcTxByteFSRate)
 
begin
 
begin
 
if (muxSIENotPTXB  == 1'b1)
 
if (muxSIENotPTXB  == 1'b1)
 
begin
 
begin
 
USBWireWEn <= SIETxWEn;
 
USBWireWEn <= SIETxWEn;
 
TxBits <= SIETxData;
 
TxBits <= SIETxData;
 
TxCtl <= SIETxCtrl;
 
TxCtl <= SIETxCtrl;
 
 
 
TxFSRate <= SIETxFSRate;
 
end
 
end
 
else
 
else
 
begin
 
begin
 
USBWireWEn <= prcTxByteWEn;
 
USBWireWEn <= prcTxByteWEn;
 
TxBits <= prcTxByteData;
 
TxBits <= prcTxByteData;
 
TxCtl <= prcTxByteCtrl;
 
TxCtl <= prcTxByteCtrl;
 
 
 
TxFSRate <= prcTxByteFSRate;
 
end
 
end
 
end
 
end
 
 
 
 
 
 
 
 
 
// Machine: txWireArb
 
// Machine: txWireArb

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