| Line 84... |
Line 84... |
wire rstSyncToBusClk;
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wire rstSyncToBusClk;
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wire [7:0] fifoDataIn;
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wire [7:0] fifoDataIn;
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wire [7:0] busDataIn;
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wire [7:0] busDataIn;
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reg [7:0] busDataOut;
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reg [7:0] busDataOut;
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reg fifoREn;
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reg fifoREn;
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reg forceEmptySyncToUsbClk;
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wire forceEmptySyncToUsbClk;
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wire forceEmptySyncToBusClk;
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wire forceEmptySyncToBusClk;
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wire [15:0] numElementsInFifo;
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wire [15:0] numElementsInFifo;
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wire fifoSelect;
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wire fifoSelect;
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reg [5:0] forceEmptyShift;
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reg forceEmptyReg;
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reg forceEmpty;
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reg forceEmpty;
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reg forceEmptySyncToUsbClkFirst;
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reg forceEmptyToggle;
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reg [2:0] forceEmptyToggleSyncToUsbClk;
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//sync write
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//sync write
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always @(posedge busClk)
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always @(posedge busClk)
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begin
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begin
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if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
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if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
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| Line 103... |
Line 104... |
forceEmpty <= 1'b1;
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forceEmpty <= 1'b1;
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else
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else
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forceEmpty <= 1'b0;
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forceEmpty <= 1'b0;
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end
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end
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//generate 'forceEmptySyncToBusClk'
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//detect rising edge of 'forceEmpty', and generate toggle signal
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//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
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always @(posedge busClk) begin
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always @(posedge busClk) begin
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if (rstSyncToBusClk == 1'b1)
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if (rstSyncToBusClk == 1'b1) begin
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forceEmptyShift <= 6'b000000;
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forceEmptyReg <= 1'b0;
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forceEmptyToggle <= 1'b0;
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end
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else begin
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else begin
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if (forceEmpty == 1'b1)
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if (forceEmpty == 1'b1)
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forceEmptyShift <= 6'b111111;
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forceEmptyReg <= 1'b1;
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else
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else
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forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
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forceEmptyReg <= 1'b0;
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if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
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forceEmptyToggle <= ~forceEmptyToggle;
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end
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end
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end
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end
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assign forceEmptySyncToBusClk = forceEmptyShift[0];
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assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
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// double sync across clock domains to generate 'forceEmptySyncToWrClk'
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// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
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always @(posedge usbClk) begin
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always @(posedge usbClk) begin
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forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
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forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
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forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
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end
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end
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assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
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// async read mux
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// async read mux
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always @(address or fifoDataIn or numElementsInFifo)
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always @(address or fifoDataIn or numElementsInFifo)
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begin
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begin
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case (address)
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case (address)
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