| Line 61... |
Line 61... |
SOFSync,
|
SOFSync,
|
TxLineState,
|
TxLineState,
|
LineDirectControlEn,
|
LineDirectControlEn,
|
fullSpeedPol,
|
fullSpeedPol,
|
fullSpeedRate,
|
fullSpeedRate,
|
transReq
|
transReq,
|
|
isoEn
|
);
|
);
|
input [3:0] address;
|
input [3:0] address;
|
input [7:0] dataIn;
|
input [7:0] dataIn;
|
input writeEn;
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input writeEn;
|
input strobe_i;
|
input strobe_i;
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| Line 96... |
Line 97... |
output [1:0] TxLineState;
|
output [1:0] TxLineState;
|
output LineDirectControlEn;
|
output LineDirectControlEn;
|
output fullSpeedPol;
|
output fullSpeedPol;
|
output fullSpeedRate;
|
output fullSpeedRate;
|
output transReq;
|
output transReq;
|
|
output isoEn; //enable isochronous mode
|
|
|
wire [3:0] address;
|
wire [3:0] address;
|
wire [7:0] dataIn;
|
wire [7:0] dataIn;
|
wire writeEn;
|
wire writeEn;
|
wire strobe_i;
|
wire strobe_i;
|
| Line 132... |
Line 134... |
reg [1:0] TxLineState;
|
reg [1:0] TxLineState;
|
reg LineDirectControlEn;
|
reg LineDirectControlEn;
|
reg fullSpeedPol;
|
reg fullSpeedPol;
|
reg fullSpeedRate;
|
reg fullSpeedRate;
|
reg transReq;
|
reg transReq;
|
|
reg isoEn;
|
|
|
//internal wire and regs
|
//internal wire and regs
|
reg [1:0] TxControlReg;
|
reg [1:0] TxControlReg;
|
reg [4:0] TxLineControlReg;
|
reg [4:0] TxLineControlReg;
|
reg clrSOFReq;
|
reg clrSOFReq;
|
| Line 150... |
Line 153... |
reg setTransReq;
|
reg setTransReq;
|
|
|
//sync write demux
|
//sync write demux
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
|
if (rst == 1'b1) begin
|
|
isoEn <= 1'b0;
|
|
preambleEn <= 1'b0;
|
|
SOFSync <= 1'b0;
|
|
TxTransTypeReg <= 2'b00;
|
|
TxLineControlReg <= 5'h00;
|
|
TxSOFEnableReg <= 1'b0;
|
|
TxAddrReg <= 7'h00;
|
|
TxEndPReg <= 4'h0;
|
|
interruptMaskReg <= 4'h0;
|
|
end
|
|
else begin
|
clrSOFReq <= 1'b0;
|
clrSOFReq <= 1'b0;
|
clrConnEvtReq <= 1'b0;
|
clrConnEvtReq <= 1'b0;
|
clrResInReq <= 1'b0;
|
clrResInReq <= 1'b0;
|
clrTransDoneReq <= 1'b0;
|
clrTransDoneReq <= 1'b0;
|
setTransReq <= 1'b0;
|
setTransReq <= 1'b0;
|
if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
|
if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : begin
|
`TX_CONTROL_REG : begin
|
preambleEn <= dataIn[2];
|
isoEn <= dataIn[`ISO_ENABLE_BIT];
|
SOFSync <= dataIn[1];
|
preambleEn <= dataIn[`PREAMBLE_ENABLE_BIT];
|
setTransReq <= dataIn[0];
|
SOFSync <= dataIn[`SOF_SYNC_BIT];
|
|
setTransReq <= dataIn[`TRANS_REQ_BIT];
|
end
|
end
|
`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
|
`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
|
`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
|
`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
|
`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
|
`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[`SOF_EN_BIT];
|
`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
|
`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
|
`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
|
`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
|
`INTERRUPT_STATUS_REG : begin
|
`INTERRUPT_STATUS_REG : begin
|
clrSOFReq <= dataIn[3];
|
clrSOFReq <= dataIn[`SOF_SENT_BIT];
|
clrConnEvtReq <= dataIn[2];
|
clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
|
clrResInReq <= dataIn[1];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrTransDoneReq <= dataIn[0];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
end
|
end
|
`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
|
`INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[3:0];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
end
|
|
|
//interrupt control
|
//interrupt control
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
|
if (rst == 1'b1) begin
|
|
SOFSentInt <= 1'b0;
|
|
connEventInt <= 1'b0;
|
|
resumeInt <= 1'b0;
|
|
transDoneInt <= 1'b0;
|
|
end
|
|
else begin
|
if (SOFSentIn == 1'b1)
|
if (SOFSentIn == 1'b1)
|
SOFSentInt <= 1'b1;
|
SOFSentInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
|
|
| Line 202... |
Line 226... |
if (transDoneIn == 1'b1)
|
if (transDoneIn == 1'b1)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
|
end
|
|
|
//mask interrupts
|
//mask interrupts
|
always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
|
always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
| Line 214... |
Line 239... |
end
|
end
|
|
|
//transaction request set/clear
|
//transaction request set/clear
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
|
if (rst == 1'b1) begin
|
|
transReq <= 1'b0;
|
|
end
|
|
else begin
|
if (setTransReq == 1'b1)
|
if (setTransReq == 1'b1)
|
transReq <= 1'b1;
|
transReq <= 1'b1;
|
else if (clrTransReq == 1'b1)
|
else if (clrTransReq == 1'b1)
|
transReq <= 1'b0;
|
transReq <= 1'b0;
|
end
|
end
|
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(TxControlReg or TxLineControlReg) begin
|
always @(TxControlReg or TxLineControlReg) begin
|
TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
| Line 234... |
Line 264... |
always @(address or
|
always @(address or
|
TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
|
TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
|
TxAddrReg or TxEndPReg or frameNumIn or
|
TxAddrReg or TxEndPReg or frameNumIn or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
|
interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
|
preambleEn or SOFSync or transReq)
|
preambleEn or SOFSync or transReq or isoEn)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEn, preambleEn, SOFSync, transReq} ;
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
|
