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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [USBHostControlBI.v] - Diff between revs 14 and 16

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Rev 14 Rev 16
Line 62... Line 62... 
  TxLineState,
 
  TxLineState,
 
  LineDirectControlEn,
 
  LineDirectControlEn,
 
  fullSpeedPol,
 
  fullSpeedPol,
 
  fullSpeedRate,
 
  fullSpeedRate,
 
  transReq,
 
  transReq,
 
  isoEn
 
  isoEn,
 
 
 
  SOFTimer
 
  );
 
  );
 
input [3:0] address;
 
input [3:0] address;
 
input [7:0] dataIn;
 
input [7:0] dataIn;
 
input writeEn;
 
input writeEn;
 
input strobe_i;
 
input strobe_i;
Line 98... Line 99... 
output LineDirectControlEn;
 
output LineDirectControlEn;
 
output fullSpeedPol;
 
output fullSpeedPol;
 
output fullSpeedRate;
 
output fullSpeedRate;
 
output transReq;
 
output transReq;
 
output isoEn;     //enable isochronous mode
 
output isoEn;     //enable isochronous mode
 
 
 
input [15:0] SOFTimer;
 
 
 
 
 
wire [3:0] address;
 
wire [3:0] address;
 
wire [7:0] dataIn;
 
wire [7:0] dataIn;
 
wire writeEn;
 
wire writeEn;
 
wire strobe_i;
 
wire strobe_i;
Line 135... Line 137... 
reg LineDirectControlEn;
 
reg LineDirectControlEn;
 
reg fullSpeedPol;
 
reg fullSpeedPol;
 
reg fullSpeedRate;
 
reg fullSpeedRate;
 
reg transReq;
 
reg transReq;
 
reg isoEn;
 
reg isoEn;
 
 
 
wire [15:0] SOFTimer;
 
 
 
 
 
//internal wire and regs
 
//internal wire and regs
 
reg [1:0] TxControlReg;
 
reg [1:0] TxControlReg;
 
reg [4:0] TxLineControlReg;
 
reg [4:0] TxLineControlReg;
 
reg clrSOFReq;
 
reg clrSOFReq;
Line 280... Line 283... 
      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
 
      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
 
      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
 
      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
 
      `RX_STATUS_REG  : dataOut <= RxPktStatusIn;
 
      `RX_STATUS_REG  : dataOut <= RxPktStatusIn;
 
      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDIn};
 
      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDIn};
 
      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
 
      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
 
 
 
      `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
 
      default: dataOut <= 8'h00;
 
      default: dataOut <= 8'h00;
 
  endcase
 
  endcase
 
end
 
end
 
 
 
 
 
 
 
 

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