| Line 46... |
Line 46... |
|
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
|
|
module USBHostControlBI (address, dataIn, dataOut, writeEn,
|
module USBHostControlBI (address, dataIn, dataOut, writeEn,
|
strobe_i,
|
strobe_i,
|
clk, rst,
|
busClk,
|
|
rstSyncToBusClk,
|
|
usbClk,
|
|
rstSyncToUsbClk,
|
SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
|
SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
|
TxTransTypeReg, TxSOFEnableReg,
|
TxTransTypeReg, TxSOFEnableReg,
|
TxAddrReg, TxEndPReg, frameNumIn,
|
TxAddrReg, TxEndPReg, frameNumIn,
|
RxPktStatusIn, RxPIDIn,
|
RxPktStatusIn, RxPIDIn,
|
connectStateIn,
|
connectStateIn,
|
| Line 69... |
Line 72... |
);
|
);
|
input [3:0] address;
|
input [3:0] address;
|
input [7:0] dataIn;
|
input [7:0] dataIn;
|
input writeEn;
|
input writeEn;
|
input strobe_i;
|
input strobe_i;
|
input clk;
|
input busClk;
|
input rst;
|
input rstSyncToBusClk;
|
|
input usbClk;
|
|
input rstSyncToUsbClk;
|
output [7:0] dataOut;
|
output [7:0] dataOut;
|
output SOFSentIntOut;
|
output SOFSentIntOut;
|
output connEventIntOut;
|
output connEventIntOut;
|
output resumeIntOut;
|
output resumeIntOut;
|
output transDoneIntOut;
|
output transDoneIntOut;
|
| Line 105... |
Line 110... |
|
|
wire [3:0] address;
|
wire [3:0] address;
|
wire [7:0] dataIn;
|
wire [7:0] dataIn;
|
wire writeEn;
|
wire writeEn;
|
wire strobe_i;
|
wire strobe_i;
|
wire clk;
|
wire busClk;
|
wire rst;
|
wire rstSyncToBusClk;
|
|
wire usbClk;
|
|
wire rstSyncToUsbClk;
|
reg [7:0] dataOut;
|
reg [7:0] dataOut;
|
|
|
reg SOFSentIntOut;
|
reg SOFSentIntOut;
|
reg connEventIntOut;
|
reg connEventIntOut;
|
reg resumeIntOut;
|
reg resumeIntOut;
|
| Line 153... |
Line 160... |
reg resumeInt;
|
reg resumeInt;
|
reg transDoneInt;
|
reg transDoneInt;
|
reg [3:0] interruptMaskReg;
|
reg [3:0] interruptMaskReg;
|
reg setTransReq;
|
reg setTransReq;
|
|
|
|
//clock domain crossing sync registers
|
|
//STB = Sync To Busclk
|
|
reg [1:0] TxTransTypeRegSTB;
|
|
reg TxSOFEnableRegSTB;
|
|
reg [6:0] TxAddrRegSTB;
|
|
reg [3:0] TxEndPRegSTB;
|
|
reg preambleEnSTB;
|
|
reg SOFSyncSTB;
|
|
reg [1:0] TxLineStateSTB;
|
|
reg LineDirectControlEnSTB;
|
|
reg fullSpeedPolSTB;
|
|
reg fullSpeedRateSTB;
|
|
reg transReqSTB;
|
|
reg isoEnSTB;
|
|
reg [10:0] frameNumInSTB;
|
|
reg [7:0] RxPktStatusInSTB;
|
|
reg [3:0] RxPIDInSTB;
|
|
reg [1:0] connectStateInSTB;
|
|
reg SOFSentInSTB;
|
|
reg connEventInSTB;
|
|
reg resumeIntInSTB;
|
|
reg transDoneInSTB;
|
|
reg clrTransReqSTB;
|
|
reg [15:0] SOFTimerSTB;
|
|
|
|
|
//sync write demux
|
//sync write demux
|
always @(posedge clk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rst == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
isoEn <= 1'b0;
|
isoEnSTB <= 1'b0;
|
preambleEn <= 1'b0;
|
preambleEnSTB <= 1'b0;
|
SOFSync <= 1'b0;
|
SOFSyncSTB <= 1'b0;
|
TxTransTypeReg <= 2'b00;
|
TxTransTypeRegSTB <= 2'b00;
|
TxLineControlReg <= 5'h00;
|
TxLineControlReg <= 5'h00;
|
TxSOFEnableReg <= 1'b0;
|
TxSOFEnableRegSTB <= 1'b0;
|
TxAddrReg <= 7'h00;
|
TxAddrRegSTB <= 7'h00;
|
TxEndPReg <= 4'h0;
|
TxEndPRegSTB <= 4'h0;
|
interruptMaskReg <= 4'h0;
|
interruptMaskReg <= 4'h0;
|
end
|
end
|
else begin
|
else begin
|
clrSOFReq <= 1'b0;
|
clrSOFReq <= 1'b0;
|
clrConnEvtReq <= 1'b0;
|
clrConnEvtReq <= 1'b0;
|
| Line 177... |
Line 210... |
setTransReq <= 1'b0;
|
setTransReq <= 1'b0;
|
if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
|
if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : begin
|
`TX_CONTROL_REG : begin
|
isoEn <= dataIn[`ISO_ENABLE_BIT];
|
isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
|
preambleEn <= dataIn[`PREAMBLE_ENABLE_BIT];
|
preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
|
SOFSync <= dataIn[`SOF_SYNC_BIT];
|
SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
|
setTransReq <= dataIn[`TRANS_REQ_BIT];
|
setTransReq <= dataIn[`TRANS_REQ_BIT];
|
end
|
end
|
`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
|
`TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
|
`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
|
`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
|
`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[`SOF_EN_BIT];
|
`TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
|
`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
|
`TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
|
`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
|
`TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
|
`INTERRUPT_STATUS_REG : begin
|
`INTERRUPT_STATUS_REG : begin
|
clrSOFReq <= dataIn[`SOF_SENT_BIT];
|
clrSOFReq <= dataIn[`SOF_SENT_BIT];
|
clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
|
clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
| Line 200... |
Line 233... |
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//interrupt control
|
//interrupt control
|
always @(posedge clk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rst == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
connEventInt <= 1'b0;
|
connEventInt <= 1'b0;
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (SOFSentIn == 1'b1)
|
if (SOFSentInSTB == 1'b1)
|
SOFSentInt <= 1'b1;
|
SOFSentInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFSentInt <= 1'b0;
|
SOFSentInt <= 1'b0;
|
|
|
if (connEventIn == 1'b1)
|
if (connEventInSTB == 1'b1)
|
connEventInt <= 1'b1;
|
connEventInt <= 1'b1;
|
else if (clrConnEvtReq == 1'b1)
|
else if (clrConnEvtReq == 1'b1)
|
connEventInt <= 1'b0;
|
connEventInt <= 1'b0;
|
|
|
if (resumeIntIn == 1'b1)
|
if (resumeIntInSTB == 1'b1)
|
resumeInt <= 1'b1;
|
resumeInt <= 1'b1;
|
else if (clrResInReq == 1'b1)
|
else if (clrResInReq == 1'b1)
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
|
|
if (transDoneIn == 1'b1)
|
if (transDoneInSTB == 1'b1)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
end
|
end
|
| Line 240... |
Line 273... |
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
|
end
|
end
|
|
|
//transaction request set/clear
|
//transaction request set/clear
|
always @(posedge clk)
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
|
//'setTransReq' must be delayed with respect to other control signals, thus
|
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
|
//domain before the transaction request is asserted.
|
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
|
//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
|
|
always @(posedge busClk)
|
begin
|
begin
|
if (rst == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
transReq <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (setTransReq == 1'b1)
|
if (setTransReq == 1'b1)
|
transReq <= 1'b1;
|
transReqSTB <= 1'b1;
|
else if (clrTransReq == 1'b1)
|
else if (clrTransReqSTB == 1'b1)
|
transReq <= 1'b0;
|
transReqSTB <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(TxControlReg or TxLineControlReg) begin
|
always @(TxControlReg or TxLineControlReg) begin
|
TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
|
LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
|
fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
|
end
|
end
|
|
|
// async read mux
|
// async read mux
|
always @(address or
|
always @(address or
|
TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
|
TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
|
TxAddrReg or TxEndPReg or frameNumIn or
|
TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
|
interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
|
preambleEn or SOFSync or transReq or isoEn)
|
preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEn, preambleEn, SOFSync, transReq} ;
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
|
`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
|
`TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
|
`TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
|
`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumIn[10:8]};
|
`FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
|
`FRAME_NUM_LSB_REG : dataOut <= frameNumIn[7:0];
|
`FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`RX_STATUS_REG : dataOut <= RxPktStatusIn;
|
`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDIn};
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//re-sync from busClk to usbClk.
|
|
always @(posedge usbClk) begin
|
|
if (rstSyncToUsbClk == 1'b1) begin
|
|
isoEn <= 1'b0;
|
|
preambleEn <= 1'b0;
|
|
SOFSync <= 1'b0;
|
|
TxTransTypeReg <= 2'b00;
|
|
TxSOFEnableReg <= 1'b0;
|
|
TxAddrReg <= 7'h00;
|
|
TxEndPReg <= 4'h0;
|
|
TxLineState <= 2'b00;
|
|
LineDirectControlEn <= 1'b0;
|
|
fullSpeedPol <= 1'b0;
|
|
fullSpeedRate <= 1'b0;
|
|
transReq <= 1'b0;
|
|
end
|
|
else begin
|
|
isoEn <= isoEnSTB;
|
|
preambleEn <= preambleEnSTB;
|
|
SOFSync <= SOFSyncSTB;
|
|
TxTransTypeReg <= TxTransTypeRegSTB;
|
|
TxSOFEnableReg <= TxSOFEnableRegSTB;
|
|
TxAddrReg <= TxAddrRegSTB;
|
|
TxEndPReg <= TxEndPRegSTB;
|
|
TxLineState <= TxLineStateSTB;
|
|
LineDirectControlEn <= LineDirectControlEnSTB;
|
|
fullSpeedPol <= fullSpeedPolSTB;
|
|
fullSpeedRate <= fullSpeedRateSTB;
|
|
transReq <= transReqSTB;
|
|
end
|
|
end
|
|
|
|
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted
|
|
//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
|
|
always @(posedge busClk) begin
|
|
frameNumInSTB <= frameNumIn;
|
|
RxPktStatusInSTB <= RxPktStatusIn;
|
|
RxPIDInSTB <= RxPIDIn;
|
|
connectStateInSTB <= connectStateIn;
|
|
SOFSentInSTB <= SOFSentIn;
|
|
connEventInSTB <= connEventIn;
|
|
resumeIntInSTB <= resumeIntIn;
|
|
transDoneInSTB <= transDoneIn;
|
|
clrTransReqSTB <= clrTransReq;
|
|
SOFTimerSTB <= SOFTimer;
|
|
end
|
|
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
