| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// from <http://www.opencores.org/lgpl.shtml> ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`timescale 1ns / 1ps
|
`include "timescale.v"
|
|
|
|
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
|
|
module USBHostControlBI (address, dataIn, dataOut, writeEn,
|
module USBHostControlBI (address, dataIn, dataOut, writeEn,
|
strobe_i,
|
strobe_i,
|
busClk,
|
busClk,
|
| Line 306... |
Line 304... |
always @(address or
|
always @(address or
|
TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
|
TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
|
TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
|
TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
SOFSentInt or connEventInt or resumeInt or transDoneInt or
|
interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
|
interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
|
preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
|
preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimerSTB)
|
begin
|
begin
|
case (address)
|
case (address)
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
|
`TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
|
`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
|
| Line 322... |
Line 320... |
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_STATUS_REG : dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`INTERRUPT_MASK_REG : dataOut <= {4'h0, interruptMaskReg};
|
`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
|
`RX_STATUS_REG : dataOut <= RxPktStatusInSTB;
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
|
`RX_PID_REG : dataOut <= {4'b0000, RxPIDInSTB};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
|
`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
|
`HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
//re-sync from busClk to usbClk.
|
//re-sync from busClk to usbClk.
|
| Line 371... |
Line 369... |
SOFSentInSTB <= SOFSentIn;
|
SOFSentInSTB <= SOFSentIn;
|
connEventInSTB <= connEventIn;
|
connEventInSTB <= connEventIn;
|
resumeIntInSTB <= resumeIntIn;
|
resumeIntInSTB <= resumeIntIn;
|
transDoneInSTB <= transDoneIn;
|
transDoneInSTB <= transDoneIn;
|
clrTransReqSTB <= clrTransReq;
|
clrTransReqSTB <= clrTransReq;
|
|
//FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
|
|
//All the other multi-bit signals will be static at the time that they are
|
|
//read, but 'SOFTimer' will not be static.
|
SOFTimerSTB <= SOFTimer;
|
SOFTimerSTB <= SOFTimer;
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
