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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [USBHostControlBI.v] - Diff between revs 22 and 37

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Rev 22 Rev 37
Line 120... Line 120... 
reg connEventIntOut;
 
reg connEventIntOut;
 
reg resumeIntOut;
 
reg resumeIntOut;
 
reg transDoneIntOut;
 
reg transDoneIntOut;
 
 
 
 
 
reg [1:0] TxTransTypeReg;
 
reg [1:0] TxTransTypeReg;
 
 
 
reg [1:0] TxTransTypeReg_reg1;
 
reg TxSOFEnableReg;
 
reg TxSOFEnableReg;
 
 
 
reg TxSOFEnableReg_reg1;
 
reg [6:0] TxAddrReg;
 
reg [6:0] TxAddrReg;
 
 
 
reg [6:0] TxAddrReg_reg1;
 
reg [3:0] TxEndPReg;
 
reg [3:0] TxEndPReg;
 
 
 
reg [3:0] TxEndPReg_reg1;
 
wire [10:0] frameNumIn;
 
wire [10:0] frameNumIn;
 
wire [7:0] RxPktStatusIn;
 
wire [7:0] RxPktStatusIn;
 
wire [3:0] RxPIDIn;
 
wire [3:0] RxPIDIn;
 
wire [1:0] connectStateIn;
 
wire [1:0] connectStateIn;
 
 
 
 
Line 135... Line 139... 
wire resumeIntIn;
 
wire resumeIntIn;
 
wire transDoneIn;
 
wire transDoneIn;
 
wire hostControlSelect;
 
wire hostControlSelect;
 
wire clrTransReq;
 
wire clrTransReq;
 
reg preambleEn;
 
reg preambleEn;
 
 
 
reg preambleEn_reg1;
 
reg SOFSync;
 
reg SOFSync;
 
 
 
reg SOFSync_reg1;
 
reg [1:0] TxLineState;
 
reg [1:0] TxLineState;
 
 
 
reg [1:0] TxLineState_reg1;
 
reg LineDirectControlEn;
 
reg LineDirectControlEn;
 
 
 
reg LineDirectControlEn_reg1;
 
reg fullSpeedPol;
 
reg fullSpeedPol;
 
 
 
reg fullSpeedPol_reg1;
 
reg fullSpeedRate;
 
reg fullSpeedRate;
 
 
 
reg fullSpeedRate_reg1;
 
reg transReq;
 
reg transReq;
 
 
 
reg transReq_reg1;
 
reg isoEn;
 
reg isoEn;
 
 
 
reg isoEn_reg1;
 
wire [15:0] SOFTimer;
 
wire [15:0] SOFTimer;
 
 
 
 
 
//internal wire and regs
 
//internal wire and regs
 
reg [1:0] TxControlReg;
 
reg [1:0] TxControlReg;
 
reg [4:0] TxLineControlReg;
 
reg [4:0] TxLineControlReg;
Line 157... Line 169... 
reg connEventInt;
 
reg connEventInt;
 
reg resumeInt;
 
reg resumeInt;
 
reg transDoneInt;
 
reg transDoneInt;
 
reg [3:0] interruptMaskReg;
 
reg [3:0] interruptMaskReg;
 
reg setTransReq;
 
reg setTransReq;
 
 
 
reg [2:0] resumeIntInExtend;
 
 
 
reg [2:0] transDoneInExtend;
 
 
 
reg [2:0] connEventInExtend;
 
 
 
reg [2:0] SOFSentInExtend;
 
 
 
reg [2:0] clrTransReqExtend;
 
 
 
 
 
//clock domain crossing sync registers
 
//clock domain crossing sync registers
 
//STB = Sync To Busclk
 
//STB = Sync To Busclk
 
reg [1:0] TxTransTypeRegSTB;
 
reg [1:0] TxTransTypeRegSTB;
 
reg TxSOFEnableRegSTB;
 
reg TxSOFEnableRegSTB;
Line 173... Line 190... 
reg fullSpeedPolSTB;
 
reg fullSpeedPolSTB;
 
reg fullSpeedRateSTB;
 
reg fullSpeedRateSTB;
 
reg transReqSTB;
 
reg transReqSTB;
 
reg isoEnSTB;
 
reg isoEnSTB;
 
reg [10:0] frameNumInSTB;
 
reg [10:0] frameNumInSTB;
 
 
 
reg [10:0] frameNumInSTB_reg1;
 
reg [7:0] RxPktStatusInSTB;
 
reg [7:0] RxPktStatusInSTB;
 
 
 
reg [7:0] RxPktStatusInSTB_reg1;
 
reg [3:0] RxPIDInSTB;
 
reg [3:0] RxPIDInSTB;
 
 
 
reg [3:0] RxPIDInSTB_reg1;
 
reg [1:0] connectStateInSTB;
 
reg [1:0] connectStateInSTB;
 
reg SOFSentInSTB;
 
reg [1:0] connectStateInSTB_reg1;
 
reg connEventInSTB;
 
reg [2:0] SOFSentInSTB;
 
reg resumeIntInSTB;
 
reg [2:0] connEventInSTB;
 
reg transDoneInSTB;
 
reg [2:0] resumeIntInSTB;
 
reg clrTransReqSTB;
 
reg [2:0] transDoneInSTB;
 
 
 
reg [2:0] clrTransReqSTB;
 
reg [15:0] SOFTimerSTB;
 
reg [15:0] SOFTimerSTB;
 
 
 
reg [15:0] SOFTimerSTB_reg1;
 
 
 
 
 
 
 
 
 
//sync write demux
 
//sync write demux
 
always @(posedge busClk)
 
always @(posedge busClk)
 
begin
 
begin
Line 240... Line 262... 
    connEventInt <= 1'b0;
 
    connEventInt <= 1'b0;
 
    resumeInt <= 1'b0;
 
    resumeInt <= 1'b0;
 
    transDoneInt <= 1'b0;
 
    transDoneInt <= 1'b0;
 
  end
 
  end
 
  else begin
 
  else begin
 
    if (SOFSentInSTB == 1'b1)
 
    if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0)
 
      SOFSentInt <= 1'b1;
 
      SOFSentInt <= 1'b1;
 
    else if (clrSOFReq == 1'b1)
 
    else if (clrSOFReq == 1'b1)
 
      SOFSentInt <= 1'b0;
 
      SOFSentInt <= 1'b0;
 
 
 
 
 
    if (connEventInSTB == 1'b1)
 
    if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0)
 
      connEventInt <= 1'b1;
 
      connEventInt <= 1'b1;
 
    else if (clrConnEvtReq == 1'b1)
 
    else if (clrConnEvtReq == 1'b1)
 
      connEventInt <= 1'b0;
 
      connEventInt <= 1'b0;
 
 
 
 
 
    if (resumeIntInSTB == 1'b1)
 
    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
 
      resumeInt <= 1'b1;
 
      resumeInt <= 1'b1;
 
    else if (clrResInReq == 1'b1)
 
    else if (clrResInReq == 1'b1)
 
      resumeInt <= 1'b0;
 
      resumeInt <= 1'b0;
 
 
 
 
 
    if (transDoneInSTB == 1'b1)
 
    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
 
      transDoneInt <= 1'b1;
 
      transDoneInt <= 1'b1;
 
    else if (clrTransDoneReq == 1'b1)
 
    else if (clrTransDoneReq == 1'b1)
 
      transDoneInt <= 1'b0;
 
      transDoneInt <= 1'b0;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
//mask interrupts
 
//mask interrupts
 
always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
 
always @(*) begin
 
  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
 
  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
 
  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
 
  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
 
  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
 
  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
 
  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
 
  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
 
end
 
end
Line 276... Line 298... 
//Since 'busClk' can be a higher freq than 'usbClk',
 
//Since 'busClk' can be a higher freq than 'usbClk',
 
//'setTransReq' must be delayed with respect to other control signals, thus
 
//'setTransReq' must be delayed with respect to other control signals, thus
 
//ensuring that control signals have been clocked through to 'usbClk' clock
 
//ensuring that control signals have been clocked through to 'usbClk' clock
 
//domain before the transaction request is asserted.
 
//domain before the transaction request is asserted.
 
//Not sure this is required because there is at least two 'usbClk' ticks between
 
//Not sure this is required because there is at least two 'usbClk' ticks between
 
//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
 
//detection of 'transReq' and sampling of related control signals.
 
always @(posedge busClk)
 
always @(posedge busClk)
 
begin
 
begin
 
  if (rstSyncToBusClk == 1'b1) begin
 
  if (rstSyncToBusClk == 1'b1) begin
 
    transReqSTB <= 1'b0;
 
    transReqSTB <= 1'b0;
 
  end
 
  end
 
  else begin
 
  else begin
 
    if (setTransReq == 1'b1)
 
    if (setTransReq == 1'b1)
 
      transReqSTB <= 1'b1;
 
      transReqSTB <= 1'b1;
 
    else if (clrTransReqSTB == 1'b1)
 
    else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0)
 
      transReqSTB <= 1'b0;
 
      transReqSTB <= 1'b0;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
//break out control signals
 
//break out control signals
 
always @(TxControlReg or TxLineControlReg) begin
 
always @(*) begin
 
  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
 
  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
 
  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
 
  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
 
  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
 
  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT];
 
  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
 
  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
 
end
 
end
 
 
 
 
 
// async read mux
 
// async read mux
 
always @(address or
 
always @(*)
 
  TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
 
 
 
  TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or
 
 
 
  SOFSentInt or connEventInt or resumeInt or transDoneInt or
 
 
 
  interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
 
 
 
  preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimerSTB)
 
 
 
begin
 
begin
 
  case (address)
 
  case (address)
 
      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
 
      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
 
      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
 
      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
 
      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
 
      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
Line 329... Line 346... 
 
 
 
 
//re-sync from busClk to usbClk. 
//re-sync from busClk to usbClk. 
always @(posedge usbClk) begin
 
always @(posedge usbClk) begin
 
  if (rstSyncToUsbClk == 1'b1) begin
 
  if (rstSyncToUsbClk == 1'b1) begin
 
    isoEn <= 1'b0;
 
    isoEn <= 1'b0;
 
 
 
    isoEn_reg1 <= 1'b0;
 
    preambleEn <= 1'b0;
 
    preambleEn <= 1'b0;
 
 
 
    preambleEn_reg1 <= 1'b0;
 
    SOFSync <= 1'b0;
 
    SOFSync <= 1'b0;
 
 
 
    SOFSync_reg1 <= 1'b0;
 
    TxTransTypeReg <= 2'b00;
 
    TxTransTypeReg <= 2'b00;
 
 
 
    TxTransTypeReg_reg1 <= 2'b00;
 
    TxSOFEnableReg <= 1'b0;
 
    TxSOFEnableReg <= 1'b0;
 
    TxAddrReg <= 7'h00;
 
    TxSOFEnableReg_reg1 <= 1'b0;
 
 
 
    TxAddrReg <= {7{1'b0}};
 
 
 
    TxAddrReg_reg1 <= {7{1'b0}};
 
    TxEndPReg <= 4'h0;
 
    TxEndPReg <= 4'h0;
 
 
 
    TxEndPReg_reg1 <= 4'h0;
 
    TxLineState <= 2'b00;
 
    TxLineState <= 2'b00;
 
 
 
    TxLineState_reg1 <= 2'b00;
 
    LineDirectControlEn <= 1'b0;
 
    LineDirectControlEn <= 1'b0;
 
 
 
    LineDirectControlEn_reg1 <= 1'b0;
 
    fullSpeedPol <= 1'b0;
 
    fullSpeedPol <= 1'b0;
 
 
 
    fullSpeedPol_reg1 <= 1'b0;
 
    fullSpeedRate <= 1'b0;
 
    fullSpeedRate <= 1'b0;
 
 
 
    fullSpeedRate_reg1 <= 1'b0;
 
    transReq <= 1'b0;
 
    transReq <= 1'b0;
 
 
 
    transReq_reg1 <= 1'b0;
 
  end
 
  end
 
  else begin
 
  else begin
 
    isoEn <= isoEnSTB;
 
    isoEn_reg1 <= isoEnSTB;
 
    preambleEn <= preambleEnSTB;
 
    isoEn <= isoEn_reg1;
 
    SOFSync <= SOFSyncSTB;
 
    preambleEn_reg1 <= preambleEnSTB;
 
    TxTransTypeReg <= TxTransTypeRegSTB;
 
    preambleEn <= preambleEn_reg1;
 
    TxSOFEnableReg <= TxSOFEnableRegSTB;
 
    SOFSync_reg1 <= SOFSyncSTB;
 
    TxAddrReg <= TxAddrRegSTB;
 
    SOFSync <= SOFSync_reg1;
 
    TxEndPReg <= TxEndPRegSTB;
 
    TxTransTypeReg_reg1 <= TxTransTypeRegSTB;
 
    TxLineState <= TxLineStateSTB;
 
    TxTransTypeReg <= TxTransTypeReg_reg1;
 
    LineDirectControlEn <= LineDirectControlEnSTB;
 
    TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB;
 
    fullSpeedPol <= fullSpeedPolSTB;
 
    TxSOFEnableReg <= TxSOFEnableReg_reg1;
 
    fullSpeedRate <= fullSpeedRateSTB;
 
    TxAddrReg_reg1 <= TxAddrRegSTB;
 
    transReq <= transReqSTB;
 
    TxAddrReg <= TxAddrReg_reg1;
 
 
 
    TxEndPReg_reg1 <= TxEndPRegSTB;
 
 
 
    TxEndPReg <= TxEndPReg_reg1;
 
 
 
    TxLineState_reg1 <= TxLineStateSTB;
 
 
 
    TxLineState <= TxLineState_reg1;
 
 
 
    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
 
 
 
    LineDirectControlEn <= LineDirectControlEn_reg1;
 
 
 
    fullSpeedPol_reg1 <= fullSpeedPolSTB;
 
 
 
    fullSpeedPol <= fullSpeedPol_reg1;
 
 
 
    fullSpeedRate_reg1 <= fullSpeedRateSTB;
 
 
 
    fullSpeedRate <= fullSpeedRate_reg1;
 
 
 
    transReq_reg1 <= transReqSTB;
 
 
 
    transReq <= transReq_reg1;
 
 
 
  end
 
 
 
end
 
 
 
 
 
 
 
//Extend  resumeIntIn etc from 1 tick to 3 ticks
 
 
 
always @(posedge usbClk) begin
 
 
 
  if (rstSyncToUsbClk == 1'b1) begin
 
 
 
    resumeIntInExtend <= 3'b000;
 
 
 
    transDoneInExtend <= 3'b000;
 
 
 
    connEventInExtend <= 3'b000;
 
 
 
    SOFSentInExtend <= 3'b000;
 
 
 
    clrTransReqExtend <= 3'b000;
 
 
 
  end
 
 
 
  else begin
 
 
 
    if (resumeIntIn == 1'b1)
 
 
 
      resumeIntInExtend <= 3'b111;
 
 
 
    else
 
 
 
      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
 
 
 
    if (transDoneIn == 1'b1)
 
 
 
      transDoneInExtend <= 3'b111;
 
 
 
    else
 
 
 
      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
 
 
 
    if (connEventIn == 1'b1)
 
 
 
      connEventInExtend <= 3'b111;
 
 
 
    else
 
 
 
      connEventInExtend <= {1'b0, connEventInExtend[2:1]};
 
 
 
    if (SOFSentIn == 1'b1)
 
 
 
      SOFSentInExtend <= 3'b111;
 
 
 
    else
 
 
 
      SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]};
 
 
 
    if (clrTransReq == 1'b1)
 
 
 
      clrTransReqExtend <= 3'b111;
 
 
 
    else
 
 
 
      clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]};
 
  end
 
  end
 
end
 
end
 
 
 
 
 
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
 
//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq
 
always @(posedge busClk) begin
 
always @(posedge busClk) begin
 
  frameNumInSTB <= frameNumIn;
 
  if (rstSyncToBusClk == 1'b1) begin
 
  RxPktStatusInSTB <= RxPktStatusIn;
 
    SOFSentInSTB <= 3'b000;
 
  RxPIDInSTB <= RxPIDIn;
 
    connEventInSTB <= 3'b000;
 
  connectStateInSTB <= connectStateIn;
 
    resumeIntInSTB <= 3'b000;
 
  SOFSentInSTB <= SOFSentIn;
 
    transDoneInSTB <= 3'b000;
 
  connEventInSTB <= connEventIn;
 
    clrTransReqSTB <= 3'b000;
 
  resumeIntInSTB <= resumeIntIn;
 
    frameNumInSTB <= {11{1'b0}};
 
  transDoneInSTB <= transDoneIn;
 
    frameNumInSTB_reg1 <= {11{1'b0}};
 
  clrTransReqSTB <= clrTransReq;
 
    RxPktStatusInSTB <= 8'h00;
 
 
 
    RxPktStatusInSTB_reg1 <= 8'h00;
 
 
 
    RxPIDInSTB <= 4'h0;
 
 
 
    RxPIDInSTB_reg1 <= 4'h0;
 
 
 
    connectStateInSTB <= 2'b00;
 
 
 
    connectStateInSTB_reg1 <= 2'b00;
 
 
 
    SOFTimerSTB <= 16'h0000;
 
 
 
    SOFTimerSTB_reg1 <= 16'h0000;
 
 
 
  end
 
 
 
  else begin
 
 
 
    frameNumInSTB_reg1 <= frameNumIn;
 
 
 
    frameNumInSTB <= frameNumInSTB_reg1;
 
 
 
    RxPktStatusInSTB_reg1 <= RxPktStatusIn;
 
 
 
    RxPktStatusInSTB <= RxPktStatusInSTB_reg1;
 
 
 
    RxPIDInSTB_reg1 <= RxPIDIn;
 
 
 
    RxPIDInSTB <= RxPIDInSTB_reg1;
 
 
 
    connectStateInSTB_reg1 <= connectStateIn;
 
 
 
    connectStateInSTB <= connectStateInSTB_reg1;
 
 
 
    SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]};
 
 
 
    connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]};
 
 
 
    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
 
 
 
    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
 
 
 
    clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]};
 
  //FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
 
  //FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
 
  //All the other multi-bit signals will be static at the time that they are
 
  //All the other multi-bit signals will be static at the time that they are
 
  //read, but 'SOFTimer' will not be static.
 
  //read, but 'SOFTimer' will not be static.
 
  SOFTimerSTB <= SOFTimer;
 
    SOFTimerSTB_reg1 <= SOFTimer;
 
 
 
    SOFTimerSTB <= SOFTimerSTB_reg1;
 
 
 
  end
 
end
 
end
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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