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// File : ../RTL/hostController/directcontrol.v
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// Generated : 10/06/06 19:35:24
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// From : ../RTL/hostController/directcontrol.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// directControl
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//// directControl
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
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module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
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input HCTxPortGnt;
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input HCTxPortRdy;
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input clk;
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input clk;
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input directControlEn;
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input directControlEn;
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input [1:0]directControlLineState;
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input [1:0]directControlLineState;
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input HCTxPortGnt;
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input HCTxPortRdy;
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input rst;
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input rst;
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output [7:0]HCTxPortCntl;
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output [7:0]HCTxPortCntl;
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output [7:0]HCTxPortData;
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output [7:0]HCTxPortData;
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output HCTxPortReq;
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output HCTxPortReq;
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output HCTxPortWEn;
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output HCTxPortWEn;
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wire clk;
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wire directControlEn;
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wire [1:0]directControlLineState;
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reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0]HCTxPortData, next_HCTxPortData;
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reg [7:0]HCTxPortData, next_HCTxPortData;
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wire HCTxPortGnt;
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wire HCTxPortGnt;
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wire HCTxPortRdy;
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wire HCTxPortRdy;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortWEn, next_HCTxPortWEn;
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reg HCTxPortWEn, next_HCTxPortWEn;
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wire clk;
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wire directControlEn;
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wire [1:0] directControlLineState;
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wire rst;
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wire rst;
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// BINARY ENCODED state machine: drctCntl
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// BINARY ENCODED state machine: drctCntl
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// State codes definitions:
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// State codes definitions:
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`define START_DC 3'b000
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`define START_DC 3'b000
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`define DRCT_CNTL_WAIT_RDY 3'b100
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`define DRCT_CNTL_WAIT_RDY 3'b100
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`define IDLE_FIN 3'b101
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`define IDLE_FIN 3'b101
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`define IDLE_WAIT_GNT 3'b110
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`define IDLE_WAIT_GNT 3'b110
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`define IDLE_WAIT_RDY 3'b111
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`define IDLE_WAIT_RDY 3'b111
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reg [2:0]CurrState_drctCntl, NextState_drctCntl;
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reg [2:0] CurrState_drctCntl;
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reg [2:0] NextState_drctCntl;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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// diagram ACTION
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// diagram ACTION
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//--------------------------------------------------------------------
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// Machine: drctCntl
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// Machine: drctCntl
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
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begin : drctCntl_NextState
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NextState_drctCntl <= CurrState_drctCntl;
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NextState_drctCntl <= CurrState_drctCntl;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_HCTxPortCntl <= HCTxPortCntl;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortReq <= HCTxPortReq;
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next_HCTxPortReq <= HCTxPortReq;
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case (CurrState_drctCntl) // synopsys parallel_case full_case
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortCntl <= HCTxPortCntl;
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case (CurrState_drctCntl)
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`START_DC:
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`START_DC:
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begin
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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end
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`CHK_DRCT_CNTL:
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`CHK_DRCT_CNTL:
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begin
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if (directControlEn == 1'b1)
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if (directControlEn == 1'b1)
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begin
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begin
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NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
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NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
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next_HCTxPortReq <= 1'b1;
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next_HCTxPortReq <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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NextState_drctCntl <= `IDLE_WAIT_GNT;
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NextState_drctCntl <= `IDLE_WAIT_GNT;
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next_HCTxPortReq <= 1'b1;
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next_HCTxPortReq <= 1'b1;
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end
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end
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end
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`DRCT_CNTL_WAIT_GNT:
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`DRCT_CNTL_WAIT_GNT:
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begin
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if (HCTxPortGnt == 1'b1)
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if (HCTxPortGnt == 1'b1)
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begin
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NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
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NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
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end
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end
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`DRCT_CNTL_CHK_LOOP:
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`DRCT_CNTL_CHK_LOOP:
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begin
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begin
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next_HCTxPortWEn <= 1'b0;
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next_HCTxPortWEn <= 1'b0;
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if (directControlEn == 1'b0)
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if (directControlEn == 1'b0)
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begin
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begin
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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next_HCTxPortReq <= 1'b0;
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next_HCTxPortReq <= 1'b0;
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end
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end
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else
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else
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begin
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NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
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NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
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end
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end
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end
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`DRCT_CNTL_WAIT_RDY:
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`DRCT_CNTL_WAIT_RDY:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
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begin
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begin
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NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
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NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= {6'b000000, directControlLineState};
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next_HCTxPortData <= {6'b000000, directControlLineState};
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next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
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next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
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end
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end
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end
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`IDLE_FIN:
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`IDLE_FIN:
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begin
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begin
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next_HCTxPortWEn <= 1'b0;
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next_HCTxPortWEn <= 1'b0;
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next_HCTxPortReq <= 1'b0;
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next_HCTxPortReq <= 1'b0;
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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NextState_drctCntl <= `CHK_DRCT_CNTL;
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end
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end
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`IDLE_WAIT_GNT:
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`IDLE_WAIT_GNT:
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begin
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if (HCTxPortGnt == 1'b1)
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if (HCTxPortGnt == 1'b1)
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begin
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NextState_drctCntl <= `IDLE_WAIT_RDY;
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NextState_drctCntl <= `IDLE_WAIT_RDY;
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end
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end
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`IDLE_WAIT_RDY:
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`IDLE_WAIT_RDY:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
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begin
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begin
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NextState_drctCntl <= `IDLE_FIN;
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NextState_drctCntl <= `IDLE_FIN;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= 8'h00;
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next_HCTxPortData <= 8'h00;
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next_HCTxPortCntl <= `TX_IDLE;
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next_HCTxPortCntl <= `TX_IDLE;
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end
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : drctCntl_CurrentState
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if (rst)
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if (rst)
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CurrState_drctCntl <= `START_DC;
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CurrState_drctCntl <= `START_DC;
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else
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else
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CurrState_drctCntl <= NextState_drctCntl;
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CurrState_drctCntl <= NextState_drctCntl;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : drctCntl_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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HCTxPortCntl <= 8'h00;
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HCTxPortCntl <= 8'h00;
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HCTxPortData <= 8'h00;
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HCTxPortData <= 8'h00;
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HCTxPortWEn <= 1'b0;
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HCTxPortWEn <= 1'b0;
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