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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [getpacket.asf] - Diff between revs 2 and 5

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Rev 2 Rev 5
Line 1... Line 1...
VERSION=1.19
VERSION=1.15
HEADER
HEADER
FILE="getpacket.asf"
FILE="getpacket.asf"
FID=406f8b6a
FID=406f8b6a
LANGUAGE=VERILOG
LANGUAGE=VERILOG
ENTITY="getPacket"
ENTITY="getPacket"
 
FRAMES=ON
FREEOID=259
FREEOID=259
"LIBRARIES=`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: getpacket.asf,v 1.2 2004-12-18 14:36:09 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
MULTIPLEARCHSTATUS=FALSE
 
SYNTHESISATTRIBUTES=TRUE
 
HEADER_PARAM="AUTHOR,Steve"
 
HEADER_PARAM="COMPANY,Base2Designs"
 
HEADER_PARAM="CREATIONDATE,3/22/2004"
 
HEADER_PARAM="TITLE,getPacket"
 
END
END
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BUNDLES
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OBJECTS
OBJECTS
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G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
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L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
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L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
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S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
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L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
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S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
Line 208... Line 215...
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I 185 0 3 Builtin InPort | 140253,265199 "" ""
L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
I 187 0 2 Builtin InPort | 140242,259912 "" ""
I 187 0 2 Builtin InPort | 140242,259912 "" ""
C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
I 190 0 2 Builtin InPort | 114408,221254 "" ""
I 190 0 130 Builtin InPort | 114408,221254 "" ""
I 191 0 2 Builtin InPort | 114421,225994 "" ""
I 191 0 130 Builtin InPort | 114421,225994 "" ""
L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
I 194 0 2 Builtin InPort | 79500,237048 "" ""
I 194 0 2 Builtin InPort | 79500,237048 "" ""
K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
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L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
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I 197 0 130 Builtin Signal | 19204,221408 "" ""
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L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
I 199 0 2 Builtin Signal | 19068,244340 "" ""
I 199 0 2 Builtin Signal | 19068,244340 "" ""
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I 201 0 2 Builtin Signal | 19380,239536 "" ""
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L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
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I 203 0 2 Builtin Signal | 19840,230756 "" ""
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L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
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I 205 0 2 Builtin Signal | 19416,234868 "" ""
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L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
I 207 0 0 Builtin OutPort | 77404,226912 "" ""
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L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
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I 209 0 2 Builtin Signal | 19024,249240 "" ""
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L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
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L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
I 215 0 2 Builtin Signal | 19024,262928 "" ""
I 215 0 2 Builtin Signal | 19024,262928 "" ""
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L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
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A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
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L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
I 222 0 2 Builtin Signal | 52956,259852 "" ""
I 222 0 130 Builtin Signal | 52956,259852 "" ""
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W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
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I 238 0 130 Builtin OutPort | 77500,221804 "" ""
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L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
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A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
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I 225 0 130 Builtin Signal | 52956,265100 "" ""
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L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
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L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
I 228 0 2 Builtin InPort | 79868,253240 "" ""
I 228 0 2 Builtin InPort | 79868,253240 "" ""
L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
I 230 0 2 Builtin OutPort | 77548,248252 "" ""
I 230 0 2 Builtin OutPort | 77548,248252 "" ""
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I 232 0 2 Builtin OutPort | 77780,242452 "" ""
I 232 0 130 Builtin OutPort | 77780,242452 "" ""
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A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
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H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700

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