| Line 45... |
Line 45... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
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module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);
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input clk;
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input clk;
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input getPacketEn;
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input getPacketEn;
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input rst;
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input rst;
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input [7:0]RXDataIn;
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input [7:0]RXDataIn;
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input RXDataValid;
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input RXDataValid;
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| Line 59... |
Line 59... |
output [7:0]RXFifoData;
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output [7:0]RXFifoData;
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output RXFifoWEn;
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output RXFifoWEn;
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output RXPacketRdy;
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output RXPacketRdy;
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output [3:0]RxPID;
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output [3:0]RxPID;
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output [7:0]RXPktStatus;
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output [7:0]RXPktStatus;
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output SIERxTimeOutEn;
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wire clk;
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wire clk;
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wire getPacketEn;
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wire getPacketEn;
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wire rst;
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wire rst;
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wire [7:0]RXDataIn;
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wire [7:0]RXDataIn;
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Line 74... |
reg RXPacketRdy, next_RXPacketRdy;
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reg RXPacketRdy, next_RXPacketRdy;
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reg [3:0]RxPID, next_RxPID;
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reg [3:0]RxPID, next_RxPID;
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reg [7:0]RXPktStatus;
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reg [7:0]RXPktStatus;
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wire [7:0]RXStreamStatusIn;
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wire [7:0]RXStreamStatusIn;
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wire SIERxTimeOut;
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wire SIERxTimeOut;
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reg SIERxTimeOutEn, next_SIERxTimeOutEn;
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// diagram signals declarations
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// diagram signals declarations
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reg ACKRxed, next_ACKRxed;
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reg ACKRxed, next_ACKRxed;
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reg bitStuffError, next_bitStuffError;
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reg bitStuffError, next_bitStuffError;
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reg CRCError, next_CRCError;
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reg CRCError, next_CRCError;
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Line 131... |
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// Machine: getPkt
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// Machine: getPkt
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
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always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)
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begin
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begin
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NextState_getPkt <= CurrState_getPkt;
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NextState_getPkt <= CurrState_getPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_RXOverflow <= RXOverflow;
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next_RXOverflow <= RXOverflow;
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next_NAKRxed <= NAKRxed;
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next_NAKRxed <= NAKRxed;
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Line 151... |
next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoData <= RXFifoData;
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next_RXFifoData <= RXFifoData;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXTimeOut <= RXTimeOut;
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next_RXTimeOut <= RXTimeOut;
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next_RxPID <= RxPID;
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next_RxPID <= RxPID;
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next_SIERxTimeOutEn <= SIERxTimeOutEn;
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case (CurrState_getPkt) // synopsys parallel_case full_case
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case (CurrState_getPkt) // synopsys parallel_case full_case
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`START_GP:
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`START_GP:
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begin
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begin
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NextState_getPkt <= `WAIT_EN;
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NextState_getPkt <= `WAIT_EN;
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end
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end
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Line 167... |
next_RXTimeOut <= 1'b0;
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next_RXTimeOut <= 1'b0;
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next_NAKRxed <= 1'b0;
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next_NAKRxed <= 1'b0;
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next_stallRxed <= 1'b0;
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next_stallRxed <= 1'b0;
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next_ACKRxed <= 1'b0;
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next_ACKRxed <= 1'b0;
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next_dataSequence <= 1'b0;
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next_dataSequence <= 1'b0;
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next_SIERxTimeOutEn <= 1'b1;
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if (SIERxTimeOut == 1'b1)
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if (SIERxTimeOut == 1'b1)
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begin
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begin
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NextState_getPkt <= `PKT_RDY;
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NextState_getPkt <= `PKT_RDY;
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next_RXTimeOut <= 1'b1;
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next_RXTimeOut <= 1'b1;
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end
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end
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Line 196... |
end
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end
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end
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end
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`WAIT_EN:
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`WAIT_EN:
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begin
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begin
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next_RXPacketRdy <= 1'b0;
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next_RXPacketRdy <= 1'b0;
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next_SIERxTimeOutEn <= 1'b0;
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if (getPacketEn == 1'b1)
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if (getPacketEn == 1'b1)
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begin
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begin
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NextState_getPkt <= `WAIT_PKT;
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NextState_getPkt <= `WAIT_PKT;
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end
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end
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end
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end
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Line 363... |
begin
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begin
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RXFifoWEn <= 1'b0;
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RXFifoWEn <= 1'b0;
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RXFifoData <= 8'h00;
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RXFifoData <= 8'h00;
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RXPacketRdy <= 1'b0;
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RXPacketRdy <= 1'b0;
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RxPID <= 4'h0;
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RxPID <= 4'h0;
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SIERxTimeOutEn <= 1'b0;
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RXOverflow <= 1'b0;
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RXOverflow <= 1'b0;
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NAKRxed <= 1'b0;
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NAKRxed <= 1'b0;
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stallRxed <= 1'b0;
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stallRxed <= 1'b0;
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ACKRxed <= 1'b0;
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ACKRxed <= 1'b0;
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RXByte <= 8'h00;
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RXByte <= 8'h00;
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Line 383... |
begin
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begin
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RXFifoWEn <= next_RXFifoWEn;
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RXFifoWEn <= next_RXFifoWEn;
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RXFifoData <= next_RXFifoData;
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RXFifoData <= next_RXFifoData;
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RXPacketRdy <= next_RXPacketRdy;
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RXPacketRdy <= next_RXPacketRdy;
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RxPID <= next_RxPID;
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RxPID <= next_RxPID;
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SIERxTimeOutEn <= next_SIERxTimeOutEn;
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RXOverflow <= next_RXOverflow;
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RXOverflow <= next_RXOverflow;
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NAKRxed <= next_NAKRxed;
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NAKRxed <= next_NAKRxed;
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stallRxed <= next_stallRxed;
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stallRxed <= next_stallRxed;
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ACKRxed <= next_ACKRxed;
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ACKRxed <= next_ACKRxed;
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RXByte <= next_RXByte;
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RXByte <= next_RXByte;
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