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// File : ../RTL/hostController/getpacket.v
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// Generated : 10/06/06 19:35:26
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// From : ../RTL/hostController/getpacket.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// getpacket
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//// getpacket
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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| Line 40... |
Line 45... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);
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module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst);
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input clk;
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input getPacketEn;
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input rst;
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input [7:0]RXDataIn;
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input [7:0]RXDataIn;
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input RXDataValid;
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input RXDataValid;
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input RXFifoFull;
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input RXFifoFull;
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input [7:0]RXStreamStatusIn;
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input [7:0]RXStreamStatusIn;
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input SIERxTimeOut; // Single cycle pulse
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input SIERxTimeOut; // Single cycle pulse
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input clk;
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input getPacketEn;
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input rst;
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output [7:0]RXFifoData;
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output [7:0]RXFifoData;
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output RXFifoWEn;
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output RXFifoWEn;
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output RXPacketRdy;
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output RXPacketRdy;
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output [3:0]RxPID;
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output [7:0]RXPktStatus;
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output [7:0]RXPktStatus;
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output [3:0] RxPID;
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output SIERxTimeOutEn;
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output SIERxTimeOutEn;
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wire clk;
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wire getPacketEn;
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wire rst;
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wire [7:0]RXDataIn;
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wire [7:0]RXDataIn;
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wire RXDataValid;
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wire RXDataValid;
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reg [7:0]RXFifoData, next_RXFifoData;
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reg [7:0]RXFifoData, next_RXFifoData;
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wire RXFifoFull;
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wire RXFifoFull;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXPacketRdy, next_RXPacketRdy;
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reg RXPacketRdy, next_RXPacketRdy;
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reg [3:0]RxPID, next_RxPID;
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reg [7:0]RXPktStatus;
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reg [7:0]RXPktStatus;
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wire [7:0]RXStreamStatusIn;
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wire [7:0]RXStreamStatusIn;
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reg [3:0] RxPID, next_RxPID;
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wire SIERxTimeOut;
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wire SIERxTimeOut;
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reg SIERxTimeOutEn, next_SIERxTimeOutEn;
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reg SIERxTimeOutEn, next_SIERxTimeOutEn;
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wire clk;
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wire getPacketEn;
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wire rst;
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// diagram signals declarations
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// diagram signals declarations
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reg ACKRxed, next_ACKRxed;
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reg ACKRxed, next_ACKRxed;
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reg bitStuffError, next_bitStuffError;
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reg CRCError, next_CRCError;
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reg CRCError, next_CRCError;
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reg dataSequence, next_dataSequence;
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reg NAKRxed, next_NAKRxed;
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reg NAKRxed, next_NAKRxed;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByteOld, next_RXByteOld;
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reg [7:0]RXByteOld, next_RXByteOld;
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reg [7:0]RXByteOldest, next_RXByteOldest;
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reg [7:0]RXByteOldest, next_RXByteOldest;
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reg [7:0]RXByte, next_RXByte;
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reg RXOverflow, next_RXOverflow;
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reg RXOverflow, next_RXOverflow;
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reg [7:0]RXStreamStatus, next_RXStreamStatus;
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reg [7:0]RXStreamStatus, next_RXStreamStatus;
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reg RXTimeOut, next_RXTimeOut;
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reg RXTimeOut, next_RXTimeOut;
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reg bitStuffError, next_bitStuffError;
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reg dataSequence, next_dataSequence;
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reg stallRxed, next_stallRxed;
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reg stallRxed, next_stallRxed;
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// BINARY ENCODED state machine: getPkt
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// BINARY ENCODED state machine: getPkt
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// State codes definitions:
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// State codes definitions:
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`define PROC_PKT_CHK_PID 5'b00000
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`define PROC_PKT_CHK_PID 5'b00000
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| Line 111... |
Line 116... |
`define CHK_PKT_START 5'b01110
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`define CHK_PKT_START 5'b01110
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`define WAIT_EN 5'b01111
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`define WAIT_EN 5'b01111
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`define PKT_RDY 5'b10000
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`define PKT_RDY 5'b10000
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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reg [4:0]CurrState_getPkt, NextState_getPkt;
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reg [4:0] CurrState_getPkt;
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reg [4:0] NextState_getPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @
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always @
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(CRCError or bitStuffError or
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(CRCError or bitStuffError or
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RXOverflow or RXTimeOut or
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RXOverflow or RXTimeOut or
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NAKRxed or stallRxed or
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NAKRxed or stallRxed or
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ACKRxed or dataSequence)
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ACKRxed or dataSequence)
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| Line 127... |
Line 134... |
stallRxed, NAKRxed,
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stallRxed, NAKRxed,
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RXTimeOut, RXOverflow,
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RXTimeOut, RXOverflow,
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bitStuffError, CRCError};
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bitStuffError, CRCError};
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end
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end
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//--------------------------------------------------------------------
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// Machine: getPkt
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// Machine: getPkt
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
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begin : getPkt_NextState
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NextState_getPkt <= CurrState_getPkt;
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NextState_getPkt <= CurrState_getPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_CRCError <= CRCError;
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next_bitStuffError <= bitStuffError;
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next_RXOverflow <= RXOverflow;
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next_RXOverflow <= RXOverflow;
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next_RXTimeOut <= RXTimeOut;
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next_NAKRxed <= NAKRxed;
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next_NAKRxed <= NAKRxed;
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next_stallRxed <= stallRxed;
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next_stallRxed <= stallRxed;
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next_ACKRxed <= ACKRxed;
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next_ACKRxed <= ACKRxed;
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next_dataSequence <= dataSequence;
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next_SIERxTimeOutEn <= SIERxTimeOutEn;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_RXStreamStatus <= RXStreamStatus;
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next_RXStreamStatus <= RXStreamStatus;
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next_RxPID <= RxPID;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXByteOldest <= RXByteOldest;
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next_RXByteOldest <= RXByteOldest;
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next_CRCError <= CRCError;
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next_bitStuffError <= bitStuffError;
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next_dataSequence <= dataSequence;
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next_RXByteOld <= RXByteOld;
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next_RXByteOld <= RXByteOld;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoData <= RXFifoData;
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next_RXFifoData <= RXFifoData;
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next_RXPacketRdy <= RXPacketRdy;
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case (CurrState_getPkt)
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next_RXTimeOut <= RXTimeOut;
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next_RxPID <= RxPID;
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next_SIERxTimeOutEn <= SIERxTimeOutEn;
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case (CurrState_getPkt) // synopsys parallel_case full_case
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`START_GP:
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`START_GP:
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begin
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NextState_getPkt <= `WAIT_EN;
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NextState_getPkt <= `WAIT_EN;
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end
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`WAIT_PKT:
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`WAIT_PKT:
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begin
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begin
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next_CRCError <= 1'b0;
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next_CRCError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_RXOverflow <= 1'b0;
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next_RXOverflow <= 1'b0;
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Line 188... |
next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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end
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`CHK_PKT_START:
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`CHK_PKT_START:
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begin
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if (RXStreamStatus == `RX_PACKET_START)
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if (RXStreamStatus == `RX_PACKET_START)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_CHK_PID;
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NextState_getPkt <= `PROC_PKT_CHK_PID;
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next_RxPID <= RXByte[3:0];
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next_RxPID <= RXByte[3:0];
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end
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end
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else
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else
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begin
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begin
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NextState_getPkt <= `PKT_RDY;
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NextState_getPkt <= `PKT_RDY;
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next_RXTimeOut <= 1'b1;
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next_RXTimeOut <= 1'b1;
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end
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end
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end
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`WAIT_EN:
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`WAIT_EN:
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begin
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begin
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next_RXPacketRdy <= 1'b0;
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next_RXPacketRdy <= 1'b0;
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next_SIERxTimeOutEn <= 1'b0;
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next_SIERxTimeOutEn <= 1'b0;
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if (getPacketEn == 1'b1)
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if (getPacketEn == 1'b1)
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begin
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NextState_getPkt <= `WAIT_PKT;
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NextState_getPkt <= `WAIT_PKT;
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end
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end
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end
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`PKT_RDY:
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`PKT_RDY:
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begin
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begin
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next_RXPacketRdy <= 1'b1;
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next_RXPacketRdy <= 1'b1;
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NextState_getPkt <= `WAIT_EN;
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NextState_getPkt <= `WAIT_EN;
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end
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end
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`PROC_PKT_CHK_PID:
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`PROC_PKT_CHK_PID:
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begin
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if (RXByte[1:0] == `HANDSHAKE)
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if (RXByte[1:0] == `HANDSHAKE)
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begin
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NextState_getPkt <= `PROC_PKT_HS;
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NextState_getPkt <= `PROC_PKT_HS;
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end
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else if (RXByte[1:0] == `DATA)
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else if (RXByte[1:0] == `DATA)
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begin
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NextState_getPkt <= `PROC_PKT_DATA_W_D1;
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NextState_getPkt <= `PROC_PKT_DATA_W_D1;
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end
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else
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else
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begin
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NextState_getPkt <= `PKT_RDY;
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NextState_getPkt <= `PKT_RDY;
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end
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end
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`PROC_PKT_HS:
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`PROC_PKT_HS:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
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begin
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NextState_getPkt <= `PKT_RDY;
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NextState_getPkt <= `PKT_RDY;
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next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
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next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
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next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
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next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
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next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
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next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
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next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
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next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
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end
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end
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end
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`PROC_PKT_DATA_W_D1:
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`PROC_PKT_DATA_W_D1:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
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next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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`PROC_PKT_DATA_CHK_D1:
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`PROC_PKT_DATA_CHK_D1:
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begin
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if (RXStreamStatus == `RX_PACKET_STREAM)
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if (RXStreamStatus == `RX_PACKET_STREAM)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_DATA_W_D2;
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NextState_getPkt <= `PROC_PKT_DATA_W_D2;
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next_RXByteOldest <= RXByte;
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next_RXByteOldest <= RXByte;
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end
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end
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else
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else
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begin
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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end
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end
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`PROC_PKT_DATA_W_D2:
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`PROC_PKT_DATA_W_D2:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
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next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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`PROC_PKT_DATA_FIN:
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`PROC_PKT_DATA_FIN:
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begin
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begin
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next_CRCError <= RXByte[`CRC_ERROR_BIT];
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next_CRCError <= RXByte[`CRC_ERROR_BIT];
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next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
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next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
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next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
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next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
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NextState_getPkt <= `PKT_RDY;
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NextState_getPkt <= `PKT_RDY;
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end
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end
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`PROC_PKT_DATA_CHK_D2:
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`PROC_PKT_DATA_CHK_D2:
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begin
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if (RXStreamStatus == `RX_PACKET_STREAM)
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if (RXStreamStatus == `RX_PACKET_STREAM)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_DATA_W_D3;
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NextState_getPkt <= `PROC_PKT_DATA_W_D3;
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next_RXByteOld <= RXByte;
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next_RXByteOld <= RXByte;
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end
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end
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else
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else
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begin
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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end
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end
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`PROC_PKT_DATA_W_D3:
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`PROC_PKT_DATA_W_D3:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
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begin
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
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NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
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next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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`PROC_PKT_DATA_CHK_D3:
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`PROC_PKT_DATA_CHK_D3:
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begin
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if (RXStreamStatus == `RX_PACKET_STREAM)
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if (RXStreamStatus == `RX_PACKET_STREAM)
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begin
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NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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end
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else
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else
|
begin
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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NextState_getPkt <= `PROC_PKT_DATA_FIN;
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end
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end
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`PROC_PKT_DATA_LOOP_CHK_FIFO:
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`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
begin
|
|
if (RXFifoFull == 1'b1)
|
if (RXFifoFull == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
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NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
next_RXOverflow <= 1'b1;
|
next_RXOverflow <= 1'b1;
|
end
|
end
|
| Line 317... |
Line 289... |
next_RXFifoWEn <= 1'b1;
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next_RXFifoWEn <= 1'b1;
|
next_RXFifoData <= RXByteOldest;
|
next_RXFifoData <= RXByteOldest;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
end
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|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
begin
|
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
end
|
|
`PROC_PKT_DATA_LOOP_W_D:
|
`PROC_PKT_DATA_LOOP_W_D:
|
begin
|
begin
|
next_RXFifoWEn <= 1'b0;
|
next_RXFifoWEn <= 1'b0;
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if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
begin
|
begin
|
| Line 339... |
Line 308... |
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
end
|
end
|
`PROC_PKT_DATA_LOOP_DELAY:
|
`PROC_PKT_DATA_LOOP_DELAY:
|
begin
|
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : getPkt_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_getPkt <= `START_GP;
|
CurrState_getPkt <= `START_GP;
|
else
|
else
|
CurrState_getPkt <= NextState_getPkt;
|
CurrState_getPkt <= NextState_getPkt;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : getPkt_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXFifoWEn <= 1'b0;
|
RXByteOld <= 8'h00;
|
RXFifoData <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXPacketRdy <= 1'b0;
|
CRCError <= 1'b0;
|
RxPID <= 4'h0;
|
bitStuffError <= 1'b0;
|
SIERxTimeOutEn <= 1'b0;
|
|
RXOverflow <= 1'b0;
|
RXOverflow <= 1'b0;
|
|
RXTimeOut <= 1'b0;
|
NAKRxed <= 1'b0;
|
NAKRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
|
dataSequence <= 1'b0;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXPacketRdy <= 1'b0;
|
CRCError <= 1'b0;
|
RXFifoWEn <= 1'b0;
|
bitStuffError <= 1'b0;
|
RXFifoData <= 8'h00;
|
dataSequence <= 1'b0;
|
RxPID <= 4'h0;
|
RXByteOld <= 8'h00;
|
SIERxTimeOutEn <= 1'b0;
|
RXTimeOut <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXFifoWEn <= next_RXFifoWEn;
|
RXByteOld <= next_RXByteOld;
|
RXFifoData <= next_RXFifoData;
|
RXByteOldest <= next_RXByteOldest;
|
RXPacketRdy <= next_RXPacketRdy;
|
CRCError <= next_CRCError;
|
RxPID <= next_RxPID;
|
bitStuffError <= next_bitStuffError;
|
SIERxTimeOutEn <= next_SIERxTimeOutEn;
|
|
RXOverflow <= next_RXOverflow;
|
RXOverflow <= next_RXOverflow;
|
|
RXTimeOut <= next_RXTimeOut;
|
NAKRxed <= next_NAKRxed;
|
NAKRxed <= next_NAKRxed;
|
stallRxed <= next_stallRxed;
|
stallRxed <= next_stallRxed;
|
ACKRxed <= next_ACKRxed;
|
ACKRxed <= next_ACKRxed;
|
|
dataSequence <= next_dataSequence;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXByteOldest <= next_RXByteOldest;
|
RXPacketRdy <= next_RXPacketRdy;
|
CRCError <= next_CRCError;
|
RXFifoWEn <= next_RXFifoWEn;
|
bitStuffError <= next_bitStuffError;
|
RXFifoData <= next_RXFifoData;
|
dataSequence <= next_dataSequence;
|
RxPID <= next_RxPID;
|
RXByteOld <= next_RXByteOld;
|
SIERxTimeOutEn <= next_SIERxTimeOutEn;
|
RXTimeOut <= next_RXTimeOut;
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
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|
