| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
|
|
//
|
//////////////////////////////////////////////////////////////////////
|
// Title : No Title
|
//// ////
|
// Design : usbhostslave
|
//// getpacket
|
// Author : Steve
|
//// ////
|
// Company : Base2Designs
|
//// This file is part of the usbhostslave opencores effort.
|
//
|
//// http://www.opencores.org/cores/usbhostslave/ ////
|
//-------------------------------------------------------------------------------------------------
|
//// ////
|
|
//// Module Description: ////
|
|
////
|
|
//// ////
|
|
//// To Do: ////
|
|
////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Steve Fielding, sfielding@base2designs.com ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\getpacket.v
|
// $Id: getpacket.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
|
// Generated : 09/22/04 06:01:21
|
|
// From : c:\projects\USBHostSlave\RTL\hostController\getpacket.asf
|
|
// By : FSM2VHDL ver. 4.0.5.2
|
|
//
|
//
|
//-------------------------------------------------------------------------------------------------
|
// CVS Revision History
|
//
|
//
|
// Description :
|
// $Log: not supported by cvs2svn $
|
//
|
//
|
//-------------------------------------------------------------------------------------------------
|
|
|
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
|
|
module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, clk, getPacketEn, rst);
|
module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
|
|
input clk;
|
|
input getPacketEn;
|
|
input rst;
|
input [7:0] RXDataIn;
|
input [7:0] RXDataIn;
|
input RXDataValid;
|
input RXDataValid;
|
input RXFifoFull;
|
input RXFifoFull;
|
input [7:0] RXStreamStatusIn;
|
input [7:0] RXStreamStatusIn;
|
input SIERxTimeOut; // Single cycle pulse
|
input SIERxTimeOut; // Single cycle pulse
|
input clk;
|
|
input getPacketEn;
|
|
input rst;
|
|
output [7:0] RXFifoData;
|
output [7:0] RXFifoData;
|
output RXFifoWEn;
|
output RXFifoWEn;
|
output RXPacketRdy;
|
output RXPacketRdy;
|
output [7:0] RXPktStatus;
|
|
output [3:0] RxPID;
|
output [3:0] RxPID;
|
|
output [7:0]RXPktStatus;
|
|
|
|
wire clk;
|
|
wire getPacketEn;
|
|
wire rst;
|
wire [7:0] RXDataIn;
|
wire [7:0] RXDataIn;
|
wire RXDataValid;
|
wire RXDataValid;
|
reg [7:0] RXFifoData, next_RXFifoData;
|
reg [7:0] RXFifoData, next_RXFifoData;
|
wire RXFifoFull;
|
wire RXFifoFull;
|
reg RXFifoWEn, next_RXFifoWEn;
|
reg RXFifoWEn, next_RXFifoWEn;
|
reg RXPacketRdy, next_RXPacketRdy;
|
reg RXPacketRdy, next_RXPacketRdy;
|
|
reg [3:0]RxPID, next_RxPID;
|
reg [7:0] RXPktStatus;
|
reg [7:0] RXPktStatus;
|
wire [7:0] RXStreamStatusIn;
|
wire [7:0] RXStreamStatusIn;
|
reg [3:0] RxPID, next_RxPID;
|
|
wire SIERxTimeOut;
|
wire SIERxTimeOut;
|
wire clk;
|
|
wire getPacketEn;
|
|
wire rst;
|
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg ACKRxed, next_ACKRxed;
|
reg ACKRxed, next_ACKRxed;
|
|
reg bitStuffError, next_bitStuffError;
|
reg CRCError, next_CRCError;
|
reg CRCError, next_CRCError;
|
|
reg dataSequence, next_dataSequence;
|
reg NAKRxed, next_NAKRxed;
|
reg NAKRxed, next_NAKRxed;
|
|
reg [7:0]RXByte, next_RXByte;
|
reg [7:0]RXByteOld, next_RXByteOld;
|
reg [7:0]RXByteOld, next_RXByteOld;
|
reg [7:0]RXByteOldest, next_RXByteOldest;
|
reg [7:0]RXByteOldest, next_RXByteOldest;
|
reg [7:0]RXByte, next_RXByte;
|
|
reg RXOverflow, next_RXOverflow;
|
reg RXOverflow, next_RXOverflow;
|
reg [7:0]RXStreamStatus, next_RXStreamStatus;
|
reg [7:0]RXStreamStatus, next_RXStreamStatus;
|
reg RXTimeOut, next_RXTimeOut;
|
reg RXTimeOut, next_RXTimeOut;
|
reg bitStuffError, next_bitStuffError;
|
|
reg dataSequence, next_dataSequence;
|
|
reg stallRxed, next_stallRxed;
|
reg stallRxed, next_stallRxed;
|
|
|
// BINARY ENCODED state machine: getPkt
|
// BINARY ENCODED state machine: getPkt
|
// State codes definitions:
|
// State codes definitions:
|
`define PROC_PKT_CHK_PID 5'b00000
|
`define PROC_PKT_CHK_PID 5'b00000
|
| Line 83... |
Line 113... |
`define CHK_PKT_START 5'b01110
|
`define CHK_PKT_START 5'b01110
|
`define WAIT_EN 5'b01111
|
`define WAIT_EN 5'b01111
|
`define PKT_RDY 5'b10000
|
`define PKT_RDY 5'b10000
|
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
|
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
|
|
|
reg [4:0] CurrState_getPkt;
|
reg [4:0]CurrState_getPkt, NextState_getPkt;
|
reg [4:0] NextState_getPkt;
|
|
|
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
always @
|
always @
|
(CRCError or bitStuffError or
|
(CRCError or bitStuffError or
|
RXOverflow or RXTimeOut or
|
RXOverflow or RXTimeOut or
|
NAKRxed or stallRxed or
|
NAKRxed or stallRxed or
|
ACKRxed or dataSequence)
|
ACKRxed or dataSequence)
|
begin
|
begin
|
RXPktStatus = {
|
RXPktStatus <= {
|
dataSequence, ACKRxed,
|
dataSequence, ACKRxed,
|
stallRxed, NAKRxed,
|
stallRxed, NAKRxed,
|
RXTimeOut, RXOverflow,
|
RXTimeOut, RXOverflow,
|
bitStuffError, CRCError};
|
bitStuffError, CRCError};
|
end
|
end
|
|
|
|
|
//--------------------------------------------------------------------
|
|
// Machine: getPkt
|
// Machine: getPkt
|
//--------------------------------------------------------------------
|
|
//----------------------------------
|
|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
|
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
|
begin
|
begin : getPkt_NextState
|
|
NextState_getPkt <= CurrState_getPkt;
|
NextState_getPkt <= CurrState_getPkt;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_CRCError <= CRCError;
|
|
next_bitStuffError <= bitStuffError;
|
|
next_RXOverflow <= RXOverflow;
|
next_RXOverflow <= RXOverflow;
|
next_RXTimeOut <= RXTimeOut;
|
|
next_NAKRxed <= NAKRxed;
|
next_NAKRxed <= NAKRxed;
|
next_stallRxed <= stallRxed;
|
next_stallRxed <= stallRxed;
|
next_ACKRxed <= ACKRxed;
|
next_ACKRxed <= ACKRxed;
|
next_dataSequence <= dataSequence;
|
|
next_RXByte <= RXByte;
|
next_RXByte <= RXByte;
|
next_RXStreamStatus <= RXStreamStatus;
|
next_RXStreamStatus <= RXStreamStatus;
|
next_RxPID <= RxPID;
|
|
next_RXPacketRdy <= RXPacketRdy;
|
|
next_RXByteOldest <= RXByteOldest;
|
next_RXByteOldest <= RXByteOldest;
|
|
next_CRCError <= CRCError;
|
|
next_bitStuffError <= bitStuffError;
|
|
next_dataSequence <= dataSequence;
|
next_RXByteOld <= RXByteOld;
|
next_RXByteOld <= RXByteOld;
|
next_RXFifoWEn <= RXFifoWEn;
|
next_RXFifoWEn <= RXFifoWEn;
|
next_RXFifoData <= RXFifoData;
|
next_RXFifoData <= RXFifoData;
|
|
next_RXPacketRdy <= RXPacketRdy;
|
|
next_RXTimeOut <= RXTimeOut;
|
|
next_RxPID <= RxPID;
|
case (CurrState_getPkt) // synopsys parallel_case full_case
|
case (CurrState_getPkt) // synopsys parallel_case full_case
|
`START_GP:
|
`START_GP:
|
|
begin
|
NextState_getPkt <= `WAIT_EN;
|
NextState_getPkt <= `WAIT_EN;
|
|
end
|
`WAIT_PKT:
|
`WAIT_PKT:
|
begin
|
begin
|
next_CRCError <= 1'b0;
|
next_CRCError <= 1'b0;
|
next_bitStuffError <= 1'b0;
|
next_bitStuffError <= 1'b0;
|
next_RXOverflow <= 1'b0;
|
next_RXOverflow <= 1'b0;
|
| Line 153... |
Line 181... |
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
end
|
end
|
`CHK_PKT_START:
|
`CHK_PKT_START:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_START)
|
if (RXStreamStatus == `RX_PACKET_START)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_CHK_PID;
|
NextState_getPkt <= `PROC_PKT_CHK_PID;
|
next_RxPID <= RXByte[3:0];
|
next_RxPID <= RXByte[3:0];
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_getPkt <= `PKT_RDY;
|
NextState_getPkt <= `PKT_RDY;
|
next_RXTimeOut <= 1'b1;
|
next_RXTimeOut <= 1'b1;
|
end
|
end
|
|
end
|
`WAIT_EN:
|
`WAIT_EN:
|
begin
|
begin
|
next_RXPacketRdy <= 1'b0;
|
next_RXPacketRdy <= 1'b0;
|
if (getPacketEn == 1'b1)
|
if (getPacketEn == 1'b1)
|
|
begin
|
NextState_getPkt <= `WAIT_PKT;
|
NextState_getPkt <= `WAIT_PKT;
|
end
|
end
|
|
end
|
`PKT_RDY:
|
`PKT_RDY:
|
begin
|
begin
|
next_RXPacketRdy <= 1'b1;
|
next_RXPacketRdy <= 1'b1;
|
NextState_getPkt <= `WAIT_EN;
|
NextState_getPkt <= `WAIT_EN;
|
end
|
end
|
`PROC_PKT_CHK_PID:
|
`PROC_PKT_CHK_PID:
|
|
begin
|
if (RXByte[1:0] == `HANDSHAKE)
|
if (RXByte[1:0] == `HANDSHAKE)
|
|
begin
|
NextState_getPkt <= `PROC_PKT_HS;
|
NextState_getPkt <= `PROC_PKT_HS;
|
|
end
|
else if (RXByte[1:0] == `DATA)
|
else if (RXByte[1:0] == `DATA)
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_W_D1;
|
NextState_getPkt <= `PROC_PKT_DATA_W_D1;
|
|
end
|
else
|
else
|
|
begin
|
NextState_getPkt <= `PKT_RDY;
|
NextState_getPkt <= `PKT_RDY;
|
|
end
|
|
end
|
`PROC_PKT_HS:
|
`PROC_PKT_HS:
|
|
begin
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PKT_RDY;
|
NextState_getPkt <= `PKT_RDY;
|
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
|
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
|
next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
|
next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
|
next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
|
next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
|
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
|
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_W_D1:
|
`PROC_PKT_DATA_W_D1:
|
|
begin
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_CHK_D1:
|
`PROC_PKT_DATA_CHK_D1:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_W_D2;
|
NextState_getPkt <= `PROC_PKT_DATA_W_D2;
|
next_RXByteOldest <= RXByte;
|
next_RXByteOldest <= RXByte;
|
end
|
end
|
else
|
else
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
|
end
|
|
end
|
`PROC_PKT_DATA_W_D2:
|
`PROC_PKT_DATA_W_D2:
|
|
begin
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_FIN:
|
`PROC_PKT_DATA_FIN:
|
begin
|
begin
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
NextState_getPkt <= `PKT_RDY;
|
NextState_getPkt <= `PKT_RDY;
|
end
|
end
|
`PROC_PKT_DATA_CHK_D2:
|
`PROC_PKT_DATA_CHK_D2:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_W_D3;
|
NextState_getPkt <= `PROC_PKT_DATA_W_D3;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
else
|
else
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
|
end
|
|
end
|
`PROC_PKT_DATA_W_D3:
|
`PROC_PKT_DATA_W_D3:
|
|
begin
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
|
NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_CHK_D3:
|
`PROC_PKT_DATA_CHK_D3:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
|
end
|
else
|
else
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
NextState_getPkt <= `PROC_PKT_DATA_FIN;
|
|
end
|
|
end
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
|
begin
|
if (RXFifoFull == 1'b1)
|
if (RXFifoFull == 1'b1)
|
begin
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
next_RXOverflow <= 1'b1;
|
next_RXOverflow <= 1'b1;
|
end
|
end
|
| Line 253... |
Line 316... |
next_RXFifoWEn <= 1'b1;
|
next_RXFifoWEn <= 1'b1;
|
next_RXFifoData <= RXByteOldest;
|
next_RXFifoData <= RXByteOldest;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
|
end
|
`PROC_PKT_DATA_LOOP_W_D:
|
`PROC_PKT_DATA_LOOP_W_D:
|
begin
|
begin
|
next_RXFifoWEn <= 1'b0;
|
next_RXFifoWEn <= 1'b0;
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
begin
|
begin
|
| Line 272... |
Line 338... |
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
end
|
end
|
`PROC_PKT_DATA_LOOP_DELAY:
|
`PROC_PKT_DATA_LOOP_DELAY:
|
|
begin
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : getPkt_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_getPkt <= `START_GP;
|
CurrState_getPkt <= `START_GP;
|
else
|
else
|
CurrState_getPkt <= NextState_getPkt;
|
CurrState_getPkt <= NextState_getPkt;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : getPkt_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXByteOld <= 8'h00;
|
RXFifoWEn <= 1'b0;
|
RXByteOldest <= 8'h00;
|
RXFifoData <= 8'h00;
|
CRCError <= 1'b0;
|
RXPacketRdy <= 1'b0;
|
bitStuffError <= 1'b0;
|
RxPID <= 4'h0;
|
RXOverflow <= 1'b0;
|
RXOverflow <= 1'b0;
|
RXTimeOut <= 1'b0;
|
|
NAKRxed <= 1'b0;
|
NAKRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
dataSequence <= 1'b0;
|
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXPacketRdy <= 1'b0;
|
RXByteOldest <= 8'h00;
|
RXFifoWEn <= 1'b0;
|
CRCError <= 1'b0;
|
RXFifoData <= 8'h00;
|
bitStuffError <= 1'b0;
|
RxPID <= 4'h0;
|
dataSequence <= 1'b0;
|
|
RXByteOld <= 8'h00;
|
|
RXTimeOut <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXByteOld <= next_RXByteOld;
|
RXFifoWEn <= next_RXFifoWEn;
|
RXByteOldest <= next_RXByteOldest;
|
RXFifoData <= next_RXFifoData;
|
CRCError <= next_CRCError;
|
RXPacketRdy <= next_RXPacketRdy;
|
bitStuffError <= next_bitStuffError;
|
RxPID <= next_RxPID;
|
RXOverflow <= next_RXOverflow;
|
RXOverflow <= next_RXOverflow;
|
RXTimeOut <= next_RXTimeOut;
|
|
NAKRxed <= next_NAKRxed;
|
NAKRxed <= next_NAKRxed;
|
stallRxed <= next_stallRxed;
|
stallRxed <= next_stallRxed;
|
ACKRxed <= next_ACKRxed;
|
ACKRxed <= next_ACKRxed;
|
dataSequence <= next_dataSequence;
|
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXPacketRdy <= next_RXPacketRdy;
|
RXByteOldest <= next_RXByteOldest;
|
RXFifoWEn <= next_RXFifoWEn;
|
CRCError <= next_CRCError;
|
RXFifoData <= next_RXFifoData;
|
bitStuffError <= next_bitStuffError;
|
RxPID <= next_RxPID;
|
dataSequence <= next_dataSequence;
|
|
RXByteOld <= next_RXByteOld;
|
|
RXTimeOut <= next_RXTimeOut;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
