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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
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module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
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input clk;
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input clk;
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input [7:0]directCntlCntl;
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input [7:0]directCntlCntl;
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// Machine: HCTxArb
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// Machine: HCTxArb
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
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always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
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begin
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begin
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NextState_HCTxArb = CurrState_HCTxArb;
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NextState_HCTxArb <= CurrState_HCTxArb;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_SOFCntlGnt <= SOFCntlGnt;
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next_SOFCntlGnt <= SOFCntlGnt;
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next_sendPacketGnt <= sendPacketGnt;
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next_sendPacketGnt <= sendPacketGnt;
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next_directCntlGnt <= directCntlGnt;
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next_directCntlGnt <= directCntlGnt;
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next_muxCntl <= muxCntl;
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next_muxCntl <= muxCntl;
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case (CurrState_HCTxArb) // synopsys parallel_case full_case
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case (CurrState_HCTxArb) // synopsys parallel_case full_case
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`START_HARB:
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`START_HARB:
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begin
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begin
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NextState_HCTxArb = `WAIT_REQ;
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NextState_HCTxArb <= `WAIT_REQ;
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end
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end
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`WAIT_REQ:
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`WAIT_REQ:
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begin
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begin
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if (SOFCntlReq == 1'b1)
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if (SOFCntlReq == 1'b1)
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begin
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begin
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NextState_HCTxArb = `SEND_SOF;
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NextState_HCTxArb <= `SEND_SOF;
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next_SOFCntlGnt <= 1'b1;
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next_SOFCntlGnt <= 1'b1;
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next_muxCntl <= `SOF_CTRL_MUX;
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next_muxCntl <= `SOF_CTRL_MUX;
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end
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end
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else if (sendPacketReq == 1'b1)
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else if (sendPacketReq == 1'b1)
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begin
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begin
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NextState_HCTxArb = `SEND_PACKET;
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NextState_HCTxArb <= `SEND_PACKET;
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next_sendPacketGnt <= 1'b1;
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next_sendPacketGnt <= 1'b1;
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next_muxCntl <= `SEND_PACKET_MUX;
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next_muxCntl <= `SEND_PACKET_MUX;
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end
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end
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else if (directCntlReq == 1'b1)
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else if (directCntlReq == 1'b1)
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begin
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begin
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NextState_HCTxArb = `DIRECT_CONTROL;
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NextState_HCTxArb <= `DIRECT_CONTROL;
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next_directCntlGnt <= 1'b1;
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next_directCntlGnt <= 1'b1;
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next_muxCntl <= `DIRECT_CTRL_MUX;
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next_muxCntl <= `DIRECT_CTRL_MUX;
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end
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end
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end
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end
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`SEND_SOF:
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`SEND_SOF:
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begin
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begin
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if (SOFCntlReq == 1'b0)
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if (SOFCntlReq == 1'b0)
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begin
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begin
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NextState_HCTxArb = `WAIT_REQ;
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NextState_HCTxArb <= `WAIT_REQ;
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next_SOFCntlGnt <= 1'b0;
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next_SOFCntlGnt <= 1'b0;
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end
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end
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end
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end
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`SEND_PACKET:
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`SEND_PACKET:
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begin
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begin
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if (sendPacketReq == 1'b0)
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if (sendPacketReq == 1'b0)
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begin
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begin
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NextState_HCTxArb = `WAIT_REQ;
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NextState_HCTxArb <= `WAIT_REQ;
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next_sendPacketGnt <= 1'b0;
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next_sendPacketGnt <= 1'b0;
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end
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end
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end
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end
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`DIRECT_CONTROL:
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`DIRECT_CONTROL:
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begin
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begin
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if (directCntlReq == 1'b0)
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if (directCntlReq == 1'b0)
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begin
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begin
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NextState_HCTxArb = `WAIT_REQ;
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NextState_HCTxArb <= `WAIT_REQ;
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next_directCntlGnt <= 1'b0;
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next_directCntlGnt <= 1'b0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst)
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if (rst)
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CurrState_HCTxArb = `START_HARB;
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CurrState_HCTxArb <= `START_HARB;
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else
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else
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CurrState_HCTxArb = NextState_HCTxArb;
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CurrState_HCTxArb <= NextState_HCTxArb;
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end
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end
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// Registered outputs logic
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// Registered outputs logic
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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SOFCntlGnt = 1'b0;
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SOFCntlGnt <= 1'b0;
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sendPacketGnt = 1'b0;
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sendPacketGnt <= 1'b0;
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directCntlGnt = 1'b0;
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directCntlGnt <= 1'b0;
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muxCntl = 2'b00;
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muxCntl <= 2'b00;
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end
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end
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else
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else
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begin
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begin
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SOFCntlGnt = next_SOFCntlGnt;
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SOFCntlGnt <= next_SOFCntlGnt;
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sendPacketGnt = next_sendPacketGnt;
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sendPacketGnt <= next_sendPacketGnt;
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directCntlGnt = next_directCntlGnt;
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directCntlGnt <= next_directCntlGnt;
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muxCntl = next_muxCntl;
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muxCntl <= next_muxCntl;
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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