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//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// hctxPortArbiter
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hctxportarbiter.v
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// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
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// Generated : 09/10/04 20:20:21
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// From : c:\projects\USBHostSlave\RTL\hostController\hctxportarbiter.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
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module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
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input [7:0] SOFCntlCntl;
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input [7:0] SOFCntlData;
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input SOFCntlReq;
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input SOFCntlWEn;
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input clk;
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input clk;
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input [7:0] directCntlCntl;
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input [7:0] directCntlCntl;
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input [7:0] directCntlData;
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input [7:0] directCntlData;
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input directCntlReq;
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input directCntlReq;
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input directCntlWEn;
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input directCntlWEn;
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input rst;
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input rst;
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input [7:0] sendPacketCntl;
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input [7:0] sendPacketCntl;
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input [7:0] sendPacketData;
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input [7:0] sendPacketData;
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input sendPacketReq;
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input sendPacketReq;
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input sendPacketWEn;
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input sendPacketWEn;
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input [7:0]SOFCntlCntl;
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input [7:0]SOFCntlData;
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input SOFCntlReq;
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input SOFCntlWEn;
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output directCntlGnt;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortData;
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output [7:0] HCTxPortData;
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output HCTxPortWEnable;
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output HCTxPortWEnable;
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output SOFCntlGnt;
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output directCntlGnt;
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output sendPacketGnt;
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output sendPacketGnt;
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output SOFCntlGnt;
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reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0] HCTxPortData, next_HCTxPortData;
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reg HCTxPortWEnable, next_HCTxPortWEnable;
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wire [7:0] SOFCntlCntl;
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wire [7:0] SOFCntlData;
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reg SOFCntlGnt, next_SOFCntlGnt;
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wire SOFCntlReq;
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wire SOFCntlWEn;
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wire clk;
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wire clk;
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wire [7:0] directCntlCntl;
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wire [7:0] directCntlCntl;
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wire [7:0] directCntlData;
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wire [7:0] directCntlData;
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reg directCntlGnt, next_directCntlGnt;
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reg directCntlGnt, next_directCntlGnt;
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wire directCntlReq;
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wire directCntlReq;
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wire directCntlWEn;
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wire directCntlWEn;
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reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0]HCTxPortData, next_HCTxPortData;
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reg HCTxPortWEnable, next_HCTxPortWEnable;
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wire rst;
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wire rst;
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wire [7:0] sendPacketCntl;
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wire [7:0] sendPacketCntl;
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wire [7:0] sendPacketData;
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wire [7:0] sendPacketData;
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reg sendPacketGnt, next_sendPacketGnt;
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reg sendPacketGnt, next_sendPacketGnt;
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wire sendPacketReq;
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wire sendPacketReq;
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wire sendPacketWEn;
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wire sendPacketWEn;
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wire [7:0]SOFCntlCntl;
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wire [7:0]SOFCntlData;
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reg SOFCntlGnt, next_SOFCntlGnt;
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wire SOFCntlReq;
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wire SOFCntlWEn;
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// Constants
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// Constants
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`define DIRECT_CTRL_MUX 2'b10
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`define DIRECT_CTRL_MUX 2'b10
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`define SEND_PACKET_MUX 2'b00
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`define SEND_PACKET_MUX 2'b00
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`define WAIT_REQ 3'b001
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`define WAIT_REQ 3'b001
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`define SEND_SOF 3'b010
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`define SEND_SOF 3'b010
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`define SEND_PACKET 3'b011
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`define SEND_PACKET 3'b011
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`define DIRECT_CONTROL 3'b100
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`define DIRECT_CONTROL 3'b100
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reg [2:0] CurrState_HCTxArb;
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reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
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reg [2:0] NextState_HCTxArb;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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// SOFController/directContol/sendPacket mux
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// SOFController/directContol/sendPacket mux
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always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
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always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
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directCntlWEn or directCntlData or directCntlCntl or
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directCntlWEn or directCntlData or directCntlCntl or
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end
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end
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endcase
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endcase
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end
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end
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//--------------------------------------------------------------------
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// Machine: HCTxArb
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// Machine: HCTxArb
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
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always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
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begin
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begin : HCTxArb_NextState
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NextState_HCTxArb = CurrState_HCTxArb;
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NextState_HCTxArb <= CurrState_HCTxArb;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_SOFCntlGnt <= SOFCntlGnt;
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next_SOFCntlGnt <= SOFCntlGnt;
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next_muxCntl <= muxCntl;
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next_sendPacketGnt <= sendPacketGnt;
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next_sendPacketGnt <= sendPacketGnt;
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next_directCntlGnt <= directCntlGnt;
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next_directCntlGnt <= directCntlGnt;
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next_muxCntl <= muxCntl;
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case (CurrState_HCTxArb) // synopsys parallel_case full_case
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case (CurrState_HCTxArb) // synopsys parallel_case full_case
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`START_HARB:
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`START_HARB:
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NextState_HCTxArb <= `WAIT_REQ;
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begin
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NextState_HCTxArb = `WAIT_REQ;
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end
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`WAIT_REQ:
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`WAIT_REQ:
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begin
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if (SOFCntlReq == 1'b1)
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if (SOFCntlReq == 1'b1)
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begin
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begin
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NextState_HCTxArb <= `SEND_SOF;
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NextState_HCTxArb = `SEND_SOF;
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next_SOFCntlGnt <= 1'b1;
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next_SOFCntlGnt <= 1'b1;
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next_muxCntl <= `SOF_CTRL_MUX;
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next_muxCntl <= `SOF_CTRL_MUX;
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end
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end
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else if (sendPacketReq == 1'b1)
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else if (sendPacketReq == 1'b1)
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begin
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begin
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NextState_HCTxArb <= `SEND_PACKET;
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NextState_HCTxArb = `SEND_PACKET;
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next_sendPacketGnt <= 1'b1;
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next_sendPacketGnt <= 1'b1;
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next_muxCntl <= `SEND_PACKET_MUX;
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next_muxCntl <= `SEND_PACKET_MUX;
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end
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end
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else if (directCntlReq == 1'b1)
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else if (directCntlReq == 1'b1)
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begin
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begin
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NextState_HCTxArb <= `DIRECT_CONTROL;
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NextState_HCTxArb = `DIRECT_CONTROL;
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next_directCntlGnt <= 1'b1;
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next_directCntlGnt <= 1'b1;
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next_muxCntl <= `DIRECT_CTRL_MUX;
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next_muxCntl <= `DIRECT_CTRL_MUX;
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end
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end
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end
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`SEND_SOF:
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`SEND_SOF:
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begin
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if (SOFCntlReq == 1'b0)
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if (SOFCntlReq == 1'b0)
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begin
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begin
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NextState_HCTxArb <= `WAIT_REQ;
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NextState_HCTxArb = `WAIT_REQ;
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next_SOFCntlGnt <= 1'b0;
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next_SOFCntlGnt <= 1'b0;
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end
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end
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end
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`SEND_PACKET:
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`SEND_PACKET:
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begin
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if (sendPacketReq == 1'b0)
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if (sendPacketReq == 1'b0)
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begin
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begin
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NextState_HCTxArb <= `WAIT_REQ;
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NextState_HCTxArb = `WAIT_REQ;
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next_sendPacketGnt <= 1'b0;
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next_sendPacketGnt <= 1'b0;
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end
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end
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end
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`DIRECT_CONTROL:
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`DIRECT_CONTROL:
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begin
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if (directCntlReq == 1'b0)
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if (directCntlReq == 1'b0)
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begin
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begin
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NextState_HCTxArb <= `WAIT_REQ;
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NextState_HCTxArb = `WAIT_REQ;
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next_directCntlGnt <= 1'b0;
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next_directCntlGnt <= 1'b0;
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end
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : HCTxArb_CurrentState
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begin
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if (rst)
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if (rst)
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CurrState_HCTxArb <= `START_HARB;
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CurrState_HCTxArb = `START_HARB;
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else
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else
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CurrState_HCTxArb <= NextState_HCTxArb;
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CurrState_HCTxArb = NextState_HCTxArb;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : HCTxArb_RegOutput
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begin
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if (rst)
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if (rst)
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begin
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begin
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muxCntl <= 2'b00;
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SOFCntlGnt = 1'b0;
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SOFCntlGnt <= 1'b0;
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sendPacketGnt = 1'b0;
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sendPacketGnt <= 1'b0;
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directCntlGnt = 1'b0;
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directCntlGnt <= 1'b0;
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muxCntl = 2'b00;
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end
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end
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else
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else
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begin
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begin
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muxCntl <= next_muxCntl;
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SOFCntlGnt = next_SOFCntlGnt;
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SOFCntlGnt <= next_SOFCntlGnt;
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sendPacketGnt = next_sendPacketGnt;
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sendPacketGnt <= next_sendPacketGnt;
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directCntlGnt = next_directCntlGnt;
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directCntlGnt <= next_directCntlGnt;
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muxCntl = next_muxCntl;
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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