Line 3... |
Line 3... |
FILE="hostcontroller.asf"
|
FILE="hostcontroller.asf"
|
FID=403fbdc7
|
FID=403fbdc7
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
|
ENTITY="hostcontroller"
|
ENTITY="hostcontroller"
|
FRAMES=ON
|
FRAMES=ON
|
FREEOID=445
|
FREEOID=455
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// hostController\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
|
END
|
END
|
BUNDLES
|
BUNDLES
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
Line 67... |
Line 67... |
L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
|
L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
|
L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
|
L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
|
F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
|
F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
|
L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
|
L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
|
A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
|
A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
|
L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
|
L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
|
I 300 0 130 Builtin InPort | 31274,222492 "" ""
|
I 300 0 130 Builtin InPort | 31274,222492 "" ""
|
L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
|
L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
|
I 298 0 2 Builtin OutPort | 29102,217674 "" ""
|
I 298 0 2 Builtin OutPort | 29102,217674 "" ""
|
A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
|
A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\n//now wait for 'transReq' to clear"
|
W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
|
W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
|
S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
|
S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
|
L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
|
L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
|
A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
|
A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
|
A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
|
A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
|
Line 130... |
Line 130... |
A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
|
A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
|
C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
|
C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
|
S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
|
S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
|
L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
|
L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
|
W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
|
W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
|
W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
|
|
88026,17883 53248,36150 43780,48625 34312,61101\
|
|
33772,117285 37441,132224 41110,147164 52980,154980\
|
|
61012,157537 69044,160095 94076,164012 106263,166770
|
|
W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
|
W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
|
W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
|
W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
|
W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
|
W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
|
W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
|
W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
|
W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
|
W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
|
Line 266... |
Line 262... |
L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
|
L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
|
S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
|
S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
|
W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
|
W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
|
W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
|
W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
|
C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
|
C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
|
|
L 445 446 0 TEXT "State Labels" | 91983,29847 1 0 0 "DEL1\n/33/"
|
|
S 446 6 151552 ELLIPSE "States" | 91983,29847 6500 6500
|
|
L 447 448 0 TEXT "State Labels" | 71118,38835 1 0 0 "DEL2\n/34/"
|
|
S 448 6 155648 ELLIPSE "States" | 71118,38835 6500 6500
|
|
W 451 6 0 294 446 BEZIER "Transitions" | 113064,28940 108490,29421 103055,29490 98481,29971
|
|
W 452 6 0 446 448 BEZIER "Transitions" | 86012,32413 83123,33616 79949,35000 77060,36203
|
|
W 454 6 0 448 41 BEZIER "Transitions" | 67046,43901 63355,51524 38215,83856 36770,94047\
|
|
35326,104238 36932,129759 42870,138987 48808,148215\
|
|
70958,159612 79745,162701 88532,165790 99731,166612\
|
|
106231,167093
|
A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
|
A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
|
S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
|
S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
|
L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
|
L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
|
I 215 66 0 Builtin Entry | 50996,240683
|
I 215 66 0 Builtin Entry | 50996,240683
|
I 216 66 0 Builtin Exit | 120308,37514
|
I 216 66 0 Builtin Exit | 120308,37514
|