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| Rev 14 |
Rev 18 |
| Line 113... |
Line 113... |
`define OUT1_WAIT_DATA1_SENT 6'b011100
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`define OUT1_WAIT_DATA1_SENT 6'b011100
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`define OUT1_WAIT_SP_RDY1 6'b011101
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`define OUT1_WAIT_SP_RDY1 6'b011101
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`define OUT1_CLR_WEN1 6'b011110
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`define OUT1_CLR_WEN1 6'b011110
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT0_CHK_ISO 6'b100000
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`define OUT0_CHK_ISO 6'b100000
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`define DEL1 6'b100001
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`define DEL2 6'b100010
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reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
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reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
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// Machine: hstCntrl
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// Machine: hstCntrl
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| Line 171... |
Line 173... |
next_sendPacketArbiterReq <= 1'b0;
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next_sendPacketArbiterReq <= 1'b0;
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NextState_hstCntrl <= `FIN;
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NextState_hstCntrl <= `FIN;
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end
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end
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`FIN:
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`FIN:
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begin
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begin
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next_transDone <= 1'b0;
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next_clearTXReq <= 1'b0;
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next_clearTXReq <= 1'b0;
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NextState_hstCntrl <= `TX_REQ;
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next_transDone <= 1'b0;
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//now wait for 'transReq' to clear
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NextState_hstCntrl <= `DEL1;
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end
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end
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`WAIT_GNT:
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`WAIT_GNT:
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begin
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begin
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if (sendPacketArbiterGnt == 1'b1)
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if (sendPacketArbiterGnt == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `CHK_TYPE;
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NextState_hstCntrl <= `CHK_TYPE;
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end
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end
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end
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end
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`DEL1:
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begin
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NextState_hstCntrl <= `DEL2;
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end
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`DEL2:
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begin
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NextState_hstCntrl <= `TX_REQ;
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end
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`SETUP_CLR_SP_WEN1:
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`SETUP_CLR_SP_WEN1:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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end
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end
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