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// File : ../RTL/hostController/hostcontroller.v
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// Generated : 10/06/06 19:35:25
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// From : ../RTL/hostController/hostcontroller.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// hostController
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//// hostController
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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| Line 40... |
Line 45... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
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module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
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input [7:0] RXStatus;
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input clk;
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input clk;
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input getPacketRdy;
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input getPacketRdy;
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input isoEn;
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input isoEn;
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input rst;
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input rst;
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input [7:0]RXStatus;
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input sendPacketArbiterGnt;
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input sendPacketArbiterGnt;
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input sendPacketRdy;
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input sendPacketRdy;
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input transReq;
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input transReq;
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input [1:0]transType;
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input [1:0]transType;
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output clearTXReq;
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output clearTXReq;
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| Line 62... |
Line 67... |
output sendPacketArbiterReq;
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output sendPacketArbiterReq;
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output [3:0]sendPacketPID;
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output [3:0]sendPacketPID;
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output sendPacketWEn;
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output sendPacketWEn;
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output transDone;
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output transDone;
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wire [7:0] RXStatus;
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reg clearTXReq, next_clearTXReq;
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reg clearTXReq, next_clearTXReq;
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wire clk;
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wire clk;
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wire getPacketRdy;
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reg getPacketREn, next_getPacketREn;
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reg getPacketREn, next_getPacketREn;
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wire getPacketRdy;
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wire isoEn;
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wire isoEn;
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wire rst;
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wire rst;
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wire [7:0]RXStatus;
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wire sendPacketArbiterGnt;
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wire sendPacketArbiterGnt;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg [3:0]sendPacketPID, next_sendPacketPID;
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reg [3:0]sendPacketPID, next_sendPacketPID;
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wire sendPacketRdy;
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wire sendPacketRdy;
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reg sendPacketWEn, next_sendPacketWEn;
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reg sendPacketWEn, next_sendPacketWEn;
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| Line 116... |
Line 121... |
`define OUT1_CLR_WEN2 6'b011111
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT0_CHK_ISO 6'b100000
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`define OUT0_CHK_ISO 6'b100000
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`define DEL1 6'b100001
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`define DEL1 6'b100001
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`define DEL2 6'b100010
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`define DEL2 6'b100010
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reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
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reg [5:0] CurrState_hstCntrl;
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reg [5:0] NextState_hstCntrl;
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//--------------------------------------------------------------------
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// Machine: hstCntrl
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// Machine: hstCntrl
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
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begin : hstCntrl_NextState
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NextState_hstCntrl <= CurrState_hstCntrl;
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NextState_hstCntrl <= CurrState_hstCntrl;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_transDone <= transDone;
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next_transDone <= transDone;
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next_clearTXReq <= clearTXReq;
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next_clearTXReq <= clearTXReq;
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next_sendPacketWEn <= sendPacketWEn;
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next_getPacketREn <= getPacketREn;
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next_getPacketREn <= getPacketREn;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketWEn <= sendPacketWEn;
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case (CurrState_hstCntrl)
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case (CurrState_hstCntrl) // synopsys parallel_case full_case
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`START_HC:
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`START_HC:
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begin
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NextState_hstCntrl <= `TX_REQ;
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NextState_hstCntrl <= `TX_REQ;
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end
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`TX_REQ:
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`TX_REQ:
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begin
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if (transReq == 1'b1)
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if (transReq == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `WAIT_GNT;
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NextState_hstCntrl <= `WAIT_GNT;
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next_sendPacketArbiterReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b1;
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end
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end
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end
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`CHK_TYPE:
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`CHK_TYPE:
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begin
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if (transType == `IN_TRANS)
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if (transType == `OUTDATA0_TRANS)
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begin
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NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
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end
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else if (transType == `IN_TRANS)
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begin
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NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
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NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
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end
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else if (transType == `OUTDATA0_TRANS)
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else if (transType == `SETUP_TRANS)
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NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
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begin
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NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
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end
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else if (transType == `OUTDATA1_TRANS)
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else if (transType == `OUTDATA1_TRANS)
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begin
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NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
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NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
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end
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else if (transType == `SETUP_TRANS)
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end
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NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
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`FLAG:
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`FLAG:
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begin
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begin
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next_transDone <= 1'b1;
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next_transDone <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b0;
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next_sendPacketArbiterReq <= 1'b0;
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| Line 179... |
Line 174... |
next_transDone <= 1'b0;
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next_transDone <= 1'b0;
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//now wait for 'transReq' to clear
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//now wait for 'transReq' to clear
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NextState_hstCntrl <= `DEL1;
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NextState_hstCntrl <= `DEL1;
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end
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end
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`WAIT_GNT:
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`WAIT_GNT:
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begin
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if (sendPacketArbiterGnt == 1'b1)
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if (sendPacketArbiterGnt == 1'b1)
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begin
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NextState_hstCntrl <= `CHK_TYPE;
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NextState_hstCntrl <= `CHK_TYPE;
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end
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end
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`DEL1:
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`DEL1:
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begin
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NextState_hstCntrl <= `DEL2;
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NextState_hstCntrl <= `DEL2;
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end
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`DEL2:
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`DEL2:
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begin
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NextState_hstCntrl <= `TX_REQ;
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NextState_hstCntrl <= `TX_REQ;
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end
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`SETUP_CLR_SP_WEN1:
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`SETUP_CLR_SP_WEN1:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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end
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end
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| Line 207... |
Line 194... |
end
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end
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`SETUP_WAIT_PKT_RXED:
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`SETUP_WAIT_PKT_RXED:
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begin
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begin
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next_getPacketREn <= 1'b0;
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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if (getPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
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end
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end
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end
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`SETUP_HC_WAIT_RDY:
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`SETUP_HC_WAIT_RDY:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `SETUP;
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next_sendPacketPID <= `SETUP;
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end
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end
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end
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`SETUP_WAIT_SETUP_SENT:
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`SETUP_WAIT_SETUP_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `DATA0;
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next_sendPacketPID <= `DATA0;
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end
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end
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end
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`SETUP_WAIT_DATA_SENT:
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`SETUP_WAIT_DATA_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
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NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
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next_getPacketREn <= 1'b1;
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next_getPacketREn <= 1'b1;
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end
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end
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end
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`IN_WAIT_DATA_RXED:
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`IN_WAIT_DATA_RXED:
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begin
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begin
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next_getPacketREn <= 1'b0;
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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if (getPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
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NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
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end
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end
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end
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`IN_CHK_FOR_ERROR:
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`IN_CHK_FOR_ERROR:
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begin
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if (isoEn == 1'b1)
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if (isoEn == 1'b1)
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begin
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NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
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end
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else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
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else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
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RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
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RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
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RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
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RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
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RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
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RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
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RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
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begin
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NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
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NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
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end
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else
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else
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begin
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NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
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end
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end
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`IN_CLR_SP_WEN2:
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`IN_CLR_SP_WEN2:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
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NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
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end
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end
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`IN_WAIT_IN_SENT:
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`IN_WAIT_IN_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
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NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
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next_getPacketREn <= 1'b1;
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next_getPacketREn <= 1'b1;
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end
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end
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end
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`IN_WAIT_SP_RDY1:
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`IN_WAIT_SP_RDY1:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `IN_CLR_SP_WEN1;
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NextState_hstCntrl <= `IN_CLR_SP_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `IN;
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next_sendPacketPID <= `IN;
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end
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end
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end
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`IN_WAIT_SP_RDY2:
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`IN_WAIT_SP_RDY2:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_hstCntrl <= `IN_CLR_SP_WEN2;
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NextState_hstCntrl <= `IN_CLR_SP_WEN2;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `ACK;
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next_sendPacketPID <= `ACK;
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end
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end
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end
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`IN_CLR_SP_WEN1:
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`IN_CLR_SP_WEN1:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `IN_WAIT_IN_SENT;
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NextState_hstCntrl <= `IN_WAIT_IN_SENT;
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end
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end
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`IN_WAIT_ACK_SENT:
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`IN_WAIT_ACK_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
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end
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end
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`OUT0_WAIT_RX_DATA:
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`OUT0_WAIT_RX_DATA:
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begin
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begin
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next_getPacketREn <= 1'b0;
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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if (getPacketRdy == 1'b1)
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begin
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NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
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end
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end
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end
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`OUT0_WAIT_DATA0_SENT:
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`OUT0_WAIT_DATA0_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
|
begin
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NextState_hstCntrl <= `OUT0_CHK_ISO;
|
NextState_hstCntrl <= `OUT0_CHK_ISO;
|
end
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end
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|
`OUT0_WAIT_OUT_SENT:
|
`OUT0_WAIT_OUT_SENT:
|
begin
|
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
|
next_sendPacketPID <= `DATA0;
|
end
|
end
|
end
|
|
`OUT0_WAIT_SP_RDY1:
|
`OUT0_WAIT_SP_RDY1:
|
begin
|
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
end
|
|
`OUT0_CLR_WEN1:
|
`OUT0_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
end
|
end
|
| Line 352... |
Line 301... |
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
|
NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
|
end
|
end
|
`OUT0_CHK_ISO:
|
`OUT0_CHK_ISO:
|
begin
|
|
if (isoEn == 1'b0)
|
if (isoEn == 1'b0)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
|
end
|
|
`OUT1_WAIT_RX_DATA:
|
`OUT1_WAIT_RX_DATA:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
begin
|
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
end
|
|
`OUT1_WAIT_OUT_SENT:
|
`OUT1_WAIT_OUT_SENT:
|
begin
|
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA1;
|
next_sendPacketPID <= `DATA1;
|
end
|
end
|
end
|
|
`OUT1_WAIT_DATA1_SENT:
|
`OUT1_WAIT_DATA1_SENT:
|
begin
|
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
|
`OUT1_WAIT_SP_RDY1:
|
`OUT1_WAIT_SP_RDY1:
|
begin
|
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
end
|
|
`OUT1_CLR_WEN1:
|
`OUT1_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
end
|
end
|
| Line 410... |
Line 347... |
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : hstCntrl_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_hstCntrl <= `START_HC;
|
CurrState_hstCntrl <= `START_HC;
|
else
|
else
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : hstCntrl_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
transDone <= 1'b0;
|
transDone <= 1'b0;
|
clearTXReq <= 1'b0;
|
clearTXReq <= 1'b0;
|
getPacketREn <= 1'b0;
|
getPacketREn <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketPID <= 4'b0;
|
|
sendPacketWEn <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
|
sendPacketPID <= 4'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
transDone <= next_transDone;
|
transDone <= next_transDone;
|
clearTXReq <= next_clearTXReq;
|
clearTXReq <= next_clearTXReq;
|
getPacketREn <= next_getPacketREn;
|
getPacketREn <= next_getPacketREn;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketPID <= next_sendPacketPID;
|
|
sendPacketWEn <= next_sendPacketWEn;
|
sendPacketWEn <= next_sendPacketWEn;
|
|
sendPacketPID <= next_sendPacketPID;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
