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// File : ../RTL/hostController/hostcontroller.v
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// Generated : 10/15/06 20:31:18
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// From : ../RTL/hostController/hostcontroller.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// hostController
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//// hostController
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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Line 78... |
reg sendPacketWEn, next_sendPacketWEn;
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reg sendPacketWEn, next_sendPacketWEn;
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reg transDone, next_transDone;
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reg transDone, next_transDone;
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wire transReq;
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wire transReq;
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wire [1:0] transType;
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wire [1:0] transType;
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// diagram signals declarations
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reg [3:0]delCnt, next_delCnt;
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// BINARY ENCODED state machine: hstCntrl
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// BINARY ENCODED state machine: hstCntrl
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// State codes definitions:
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// State codes definitions:
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`define START_HC 6'b000000
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`define START_HC 6'b000000
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`define TX_REQ 6'b000001
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`define TX_REQ 6'b000001
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`define CHK_TYPE 6'b000010
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`define CHK_TYPE 6'b000010
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`define OUT1_WAIT_DATA1_SENT 6'b011100
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`define OUT1_WAIT_DATA1_SENT 6'b011100
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`define OUT1_WAIT_SP_RDY1 6'b011101
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`define OUT1_WAIT_SP_RDY1 6'b011101
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`define OUT1_CLR_WEN1 6'b011110
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`define OUT1_CLR_WEN1 6'b011110
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT1_CLR_WEN2 6'b011111
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`define OUT0_CHK_ISO 6'b100000
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`define OUT0_CHK_ISO 6'b100000
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`define DEL1 6'b100001
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`define DEL2 6'b100010
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reg [5:0] CurrState_hstCntrl;
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reg [5:0] CurrState_hstCntrl;
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reg [5:0] NextState_hstCntrl;
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reg [5:0] NextState_hstCntrl;
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// Machine: hstCntrl
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// Machine: hstCntrl
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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//----------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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// Next State Logic (combinatorial)
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//----------------------------------
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//----------------------------------
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always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
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always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
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begin : hstCntrl_NextState
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begin : hstCntrl_NextState
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NextState_hstCntrl <= CurrState_hstCntrl;
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NextState_hstCntrl <= CurrState_hstCntrl;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_transDone <= transDone;
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next_transDone <= transDone;
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next_clearTXReq <= clearTXReq;
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next_clearTXReq <= clearTXReq;
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next_delCnt <= delCnt;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketWEn <= sendPacketWEn;
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next_getPacketREn <= getPacketREn;
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next_getPacketREn <= getPacketREn;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketPID <= sendPacketPID;
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case (CurrState_hstCntrl)
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case (CurrState_hstCntrl) // synopsys parallel_case full_case
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`START_HC:
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`START_HC:
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NextState_hstCntrl <= `TX_REQ;
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NextState_hstCntrl <= `TX_REQ;
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`TX_REQ:
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`TX_REQ:
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if (transReq == 1'b1)
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if (transReq == 1'b1)
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begin
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begin
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Line 161... |
`FLAG:
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`FLAG:
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begin
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begin
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next_transDone <= 1'b1;
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next_transDone <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b0;
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next_sendPacketArbiterReq <= 1'b0;
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next_delCnt <= 4'h0;
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NextState_hstCntrl <= `FIN;
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NextState_hstCntrl <= `FIN;
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end
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end
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`FIN:
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`FIN:
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begin
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begin
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next_clearTXReq <= 1'b0;
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next_clearTXReq <= 1'b0;
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next_transDone <= 1'b0;
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next_transDone <= 1'b0;
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next_delCnt <= delCnt + 1'b1;
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//now wait for 'transReq' to clear
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//now wait for 'transReq' to clear
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NextState_hstCntrl <= `DEL1;
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if (delCnt == 4'hf)
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NextState_hstCntrl <= `TX_REQ;
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end
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end
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`WAIT_GNT:
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`WAIT_GNT:
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if (sendPacketArbiterGnt == 1'b1)
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if (sendPacketArbiterGnt == 1'b1)
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NextState_hstCntrl <= `CHK_TYPE;
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NextState_hstCntrl <= `CHK_TYPE;
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`DEL1:
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NextState_hstCntrl <= `DEL2;
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`DEL2:
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NextState_hstCntrl <= `TX_REQ;
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`SETUP_CLR_SP_WEN1:
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`SETUP_CLR_SP_WEN1:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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end
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end
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//----------------------------------
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : hstCntrl_RegOutput
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begin : hstCntrl_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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delCnt <= 4'h0;
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transDone <= 1'b0;
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transDone <= 1'b0;
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clearTXReq <= 1'b0;
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clearTXReq <= 1'b0;
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getPacketREn <= 1'b0;
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getPacketREn <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketPID <= 4'b0;
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sendPacketPID <= 4'b0;
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end
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end
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else
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else
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begin
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begin
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delCnt <= next_delCnt;
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transDone <= next_transDone;
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transDone <= next_transDone;
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clearTXReq <= next_clearTXReq;
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clearTXReq <= next_clearTXReq;
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getPacketREn <= next_getPacketREn;
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getPacketREn <= next_getPacketREn;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketPID <= next_sendPacketPID;
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sendPacketPID <= next_sendPacketPID;
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end
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end
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end
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end
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endmodule
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endmodule
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