| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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|
//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// hostController
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// Author :
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//// ////
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// Company :
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hostcontroller.v
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// $Id: hostcontroller.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
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// Generated : 09/14/04 22:52:06
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// From : c:\projects\USBHostSlave\RTL\hostController\hostcontroller.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
|
module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
|
input [7:0] RXStatus;
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input clk;
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input clk;
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input getPacketRdy;
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input getPacketRdy;
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input rst;
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input rst;
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input [7:0]RXStatus;
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input sendPacketArbiterGnt;
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input sendPacketArbiterGnt;
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input sendPacketRdy;
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input sendPacketRdy;
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input transReq;
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input transReq;
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input [1:0] transType;
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input [1:0] transType;
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output clearTXReq;
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output clearTXReq;
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| Line 37... |
Line 67... |
output sendPacketArbiterReq;
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output sendPacketArbiterReq;
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output [3:0] sendPacketPID;
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output [3:0] sendPacketPID;
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output sendPacketWEn;
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output sendPacketWEn;
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output transDone;
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output transDone;
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|
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wire [7:0] RXStatus;
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reg clearTXReq, next_clearTXReq;
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reg clearTXReq, next_clearTXReq;
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wire clk;
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wire clk;
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reg getPacketREn, next_getPacketREn;
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wire getPacketRdy;
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wire getPacketRdy;
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reg getPacketREn, next_getPacketREn;
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wire rst;
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wire rst;
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wire [7:0]RXStatus;
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wire sendPacketArbiterGnt;
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wire sendPacketArbiterGnt;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg [3:0] sendPacketPID, next_sendPacketPID;
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reg [3:0] sendPacketPID, next_sendPacketPID;
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wire sendPacketRdy;
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wire sendPacketRdy;
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reg sendPacketWEn, next_sendPacketWEn;
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reg sendPacketWEn, next_sendPacketWEn;
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| Line 87... |
Line 117... |
`define OUT1_WAIT_DATA1_SENT 5'b11100
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`define OUT1_WAIT_DATA1_SENT 5'b11100
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`define OUT1_WAIT_SP_RDY1 5'b11101
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`define OUT1_WAIT_SP_RDY1 5'b11101
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`define OUT1_CLR_WEN1 5'b11110
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`define OUT1_CLR_WEN1 5'b11110
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`define OUT1_CLR_WEN2 5'b11111
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`define OUT1_CLR_WEN2 5'b11111
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|
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reg [4:0] CurrState_hstCntrl;
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reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
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reg [4:0] NextState_hstCntrl;
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|
|
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//--------------------------------------------------------------------
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|
// Machine: hstCntrl
|
// Machine: hstCntrl
|
//--------------------------------------------------------------------
|
|
//----------------------------------
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|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
|
always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
|
begin
|
begin : hstCntrl_NextState
|
|
NextState_hstCntrl <= CurrState_hstCntrl;
|
NextState_hstCntrl <= CurrState_hstCntrl;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_transDone <= transDone;
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next_transDone <= transDone;
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next_clearTXReq <= clearTXReq;
|
next_clearTXReq <= clearTXReq;
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next_sendPacketWEn <= sendPacketWEn;
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next_getPacketREn <= getPacketREn;
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next_getPacketREn <= getPacketREn;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketWEn <= sendPacketWEn;
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case (CurrState_hstCntrl) // synopsys parallel_case full_case
|
case (CurrState_hstCntrl) // synopsys parallel_case full_case
|
`START_HC:
|
`START_HC:
|
|
begin
|
NextState_hstCntrl <= `TX_REQ;
|
NextState_hstCntrl <= `TX_REQ;
|
|
end
|
`TX_REQ:
|
`TX_REQ:
|
|
begin
|
if (transReq == 1'b1)
|
if (transReq == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `WAIT_GNT;
|
NextState_hstCntrl <= `WAIT_GNT;
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next_sendPacketArbiterReq <= 1'b1;
|
next_sendPacketArbiterReq <= 1'b1;
|
end
|
end
|
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end
|
`CHK_TYPE:
|
`CHK_TYPE:
|
|
begin
|
if (transType == `IN_TRANS)
|
if (transType == `IN_TRANS)
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|
begin
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
|
|
end
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else if (transType == `OUTDATA0_TRANS)
|
else if (transType == `OUTDATA0_TRANS)
|
|
begin
|
NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
|
NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
|
|
end
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else if (transType == `OUTDATA1_TRANS)
|
else if (transType == `OUTDATA1_TRANS)
|
|
begin
|
NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
|
NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
|
|
end
|
else if (transType == `SETUP_TRANS)
|
else if (transType == `SETUP_TRANS)
|
|
begin
|
NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
|
NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
|
|
end
|
|
end
|
`FLAG:
|
`FLAG:
|
begin
|
begin
|
next_transDone <= 1'b1;
|
next_transDone <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_clearTXReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b0;
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next_sendPacketArbiterReq <= 1'b0;
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| Line 139... |
Line 179... |
next_transDone <= 1'b0;
|
next_transDone <= 1'b0;
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next_clearTXReq <= 1'b0;
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next_clearTXReq <= 1'b0;
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NextState_hstCntrl <= `TX_REQ;
|
NextState_hstCntrl <= `TX_REQ;
|
end
|
end
|
`WAIT_GNT:
|
`WAIT_GNT:
|
|
begin
|
if (sendPacketArbiterGnt == 1'b1)
|
if (sendPacketArbiterGnt == 1'b1)
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|
begin
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NextState_hstCntrl <= `CHK_TYPE;
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NextState_hstCntrl <= `CHK_TYPE;
|
|
end
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|
end
|
`SETUP_CLR_SP_WEN1:
|
`SETUP_CLR_SP_WEN1:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
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NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
|
end
|
end
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| Line 155... |
Line 199... |
end
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end
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`SETUP_WAIT_PKT_RXED:
|
`SETUP_WAIT_PKT_RXED:
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begin
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begin
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next_getPacketREn <= 1'b0;
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next_getPacketREn <= 1'b0;
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if (getPacketRdy == 1'b1)
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if (getPacketRdy == 1'b1)
|
|
begin
|
NextState_hstCntrl <= `FLAG;
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NextState_hstCntrl <= `FLAG;
|
end
|
end
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end
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`SETUP_HC_WAIT_RDY:
|
`SETUP_HC_WAIT_RDY:
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|
begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
|
begin
|
begin
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
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NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `SETUP;
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next_sendPacketPID <= `SETUP;
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end
|
end
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end
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`SETUP_WAIT_SETUP_SENT:
|
`SETUP_WAIT_SETUP_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
|
NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
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next_sendPacketPID <= `DATA0;
|
end
|
end
|
|
end
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`SETUP_WAIT_DATA_SENT:
|
`SETUP_WAIT_DATA_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
|
NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
|
end
|
`IN_WAIT_DATA_RXED:
|
`IN_WAIT_DATA_RXED:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
|
begin
|
NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
|
NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
|
end
|
end
|
|
end
|
`IN_CHK_FOR_ERROR:
|
`IN_CHK_FOR_ERROR:
|
|
begin
|
if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
|
if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
|
RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
|
RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
|
RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
|
|
begin
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
|
NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
|
|
end
|
else
|
else
|
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
|
end
|
|
end
|
`IN_CLR_SP_WEN2:
|
`IN_CLR_SP_WEN2:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
|
NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
|
end
|
end
|
`IN_WAIT_IN_SENT:
|
`IN_WAIT_IN_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
|
NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
|
end
|
`IN_WAIT_SP_RDY1:
|
`IN_WAIT_SP_RDY1:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_CLR_SP_WEN1;
|
NextState_hstCntrl <= `IN_CLR_SP_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `IN;
|
next_sendPacketPID <= `IN;
|
end
|
end
|
|
end
|
`IN_WAIT_SP_RDY2:
|
`IN_WAIT_SP_RDY2:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `IN_CLR_SP_WEN2;
|
NextState_hstCntrl <= `IN_CLR_SP_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `ACK;
|
next_sendPacketPID <= `ACK;
|
end
|
end
|
|
end
|
`IN_CLR_SP_WEN1:
|
`IN_CLR_SP_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `IN_WAIT_IN_SENT;
|
NextState_hstCntrl <= `IN_WAIT_IN_SENT;
|
end
|
end
|
`IN_WAIT_ACK_SENT:
|
`IN_WAIT_ACK_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
|
end
|
|
end
|
`OUT0_WAIT_RX_DATA:
|
`OUT0_WAIT_RX_DATA:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
|
end
|
`OUT0_WAIT_DATA0_SENT:
|
`OUT0_WAIT_DATA0_SENT:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`OUT0_WAIT_OUT_SENT:
|
`OUT0_WAIT_OUT_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
NextState_hstCntrl <= `OUT0_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
|
next_sendPacketPID <= `DATA0;
|
end
|
end
|
|
end
|
`OUT0_WAIT_SP_RDY1:
|
`OUT0_WAIT_SP_RDY1:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
NextState_hstCntrl <= `OUT0_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
|
end
|
`OUT0_CLR_WEN1:
|
`OUT0_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
|
end
|
end
|
| Line 269... |
Line 345... |
end
|
end
|
`OUT1_WAIT_RX_DATA:
|
`OUT1_WAIT_RX_DATA:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if (getPacketRdy == 1'b1)
|
if (getPacketRdy == 1'b1)
|
|
begin
|
NextState_hstCntrl <= `FLAG;
|
NextState_hstCntrl <= `FLAG;
|
end
|
end
|
|
end
|
`OUT1_WAIT_OUT_SENT:
|
`OUT1_WAIT_OUT_SENT:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
NextState_hstCntrl <= `OUT1_CLR_WEN2;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA1;
|
next_sendPacketPID <= `DATA1;
|
end
|
end
|
|
end
|
`OUT1_WAIT_DATA1_SENT:
|
`OUT1_WAIT_DATA1_SENT:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
end
|
end
|
`OUT1_WAIT_SP_RDY1:
|
`OUT1_WAIT_SP_RDY1:
|
|
begin
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
NextState_hstCntrl <= `OUT1_CLR_WEN1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `OUT;
|
next_sendPacketPID <= `OUT;
|
end
|
end
|
|
end
|
`OUT1_CLR_WEN1:
|
`OUT1_CLR_WEN1:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
|
end
|
end
|
| Line 307... |
Line 389... |
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : hstCntrl_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_hstCntrl <= `START_HC;
|
CurrState_hstCntrl <= `START_HC;
|
else
|
else
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
CurrState_hstCntrl <= NextState_hstCntrl;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : hstCntrl_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
transDone <= 1'b0;
|
transDone <= 1'b0;
|
clearTXReq <= 1'b0;
|
clearTXReq <= 1'b0;
|
getPacketREn <= 1'b0;
|
getPacketREn <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
|
sendPacketPID <= 4'b0;
|
sendPacketPID <= 4'b0;
|
|
sendPacketWEn <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
transDone <= next_transDone;
|
transDone <= next_transDone;
|
clearTXReq <= next_clearTXReq;
|
clearTXReq <= next_clearTXReq;
|
getPacketREn <= next_getPacketREn;
|
getPacketREn <= next_getPacketREn;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketWEn <= next_sendPacketWEn;
|
|
sendPacketPID <= next_sendPacketPID;
|
sendPacketPID <= next_sendPacketPID;
|
|
sendPacketWEn <= next_sendPacketWEn;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
