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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Diff between revs 5 and 7

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Rev 5 Rev 7
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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// $Id: hostcontroller.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
//
//
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        next_sendPacketArbiterReq <= 1'b1;
        next_sendPacketArbiterReq <= 1'b1;
      end
      end
    end
    end
    `CHK_TYPE:
    `CHK_TYPE:
    begin
    begin
      if (transType == `IN_TRANS)
      if (transType == `OUTDATA0_TRANS)
      begin
 
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
 
      end
 
      else if (transType == `OUTDATA0_TRANS)
 
      begin
      begin
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      end
      end
      else if (transType == `OUTDATA1_TRANS)
      else if (transType == `IN_TRANS)
      begin
      begin
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      end
      end
      else if (transType == `SETUP_TRANS)
      else if (transType == `SETUP_TRANS)
      begin
      begin
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
      end
      end
 
      else if (transType == `OUTDATA1_TRANS)
 
      begin
 
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
 
      end
    end
    end
    `FLAG:
    `FLAG:
    begin
    begin
      next_transDone <= 1'b1;
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_clearTXReq <= 1'b1;

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