OpenCores

Rev 7	Rev 9
Line 40...	Line 40...
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $`
`//`
`// CVS Revision History`
`//`
`// $Log: not supported by cvs2svn $`
`//`
`timescale 1ns / 1ps	`timescale 1ns / 1ps
`include "usbHostControl_h.v"	`include "usbHostControl_h.v"
`include "usbConstants_h.v"	`include "usbConstants_h.v"


Line 148...	Line 142...
`next_sendPacketArbiterReq <= 1'b1;`	`next_sendPacketArbiterReq <= 1'b1;`
`end`	`end`
`end`	`end`
`CHK_TYPE:	`CHK_TYPE:
`begin`	`begin`
if (transType == `OUTDATA0_TRANS)	if (transType == `IN_TRANS)
`begin`
NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
`end`
else if (transType == `IN_TRANS)
`begin`	`begin`
NextState_hstCntrl <= `IN_WAIT_SP_RDY1;	NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
`end`	`end`
else if (transType == `SETUP_TRANS)	else if (transType == `OUTDATA0_TRANS)
`begin`	`begin`
NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;	NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
`end`	`end`
else if (transType == `OUTDATA1_TRANS)	else if (transType == `OUTDATA1_TRANS)
`begin`	`begin`
NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;	NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
`end`	`end`
	else if (transType == `SETUP_TRANS)
	`begin`
	NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
	`end`
`end`	`end`
`FLAG:	`FLAG:
`begin`	`begin`
`next_transDone <= 1'b1;`	`next_transDone <= 1'b1;`
`next_clearTXReq <= 1'b1;`	`next_clearTXReq <= 1'b1;`
Line 306...	Line 300...
NextState_hstCntrl <= `FLAG;	NextState_hstCntrl <= `FLAG;
`end`	`end`
`end`	`end`
`OUT0_WAIT_DATA0_SENT:	`OUT0_WAIT_DATA0_SENT:
`begin`	`begin`
`next_sendPacketWEn <= 1'b0;`
`if (sendPacketRdy == 1'b1)`	`if (sendPacketRdy == 1'b1)`
`begin`	`begin`
NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;	NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
`next_getPacketREn <= 1'b1;`	`next_getPacketREn <= 1'b1;`
`end`	`end`
Line 360...	Line 353...
next_sendPacketPID <= `DATA1;	next_sendPacketPID <= `DATA1;
`end`	`end`
`end`	`end`
`OUT1_WAIT_DATA1_SENT:	`OUT1_WAIT_DATA1_SENT:
`begin`	`begin`
`next_sendPacketWEn <= 1'b0;`
`if (sendPacketRdy == 1'b1)`	`if (sendPacketRdy == 1'b1)`
`begin`	`begin`
NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;	NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
`next_getPacketREn <= 1'b1;`	`next_getPacketREn <= 1'b1;`
`end`	`end`

Line 40...

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`timescale 1ns / 1ps

`timescale 1ns / 1ps

`include "usbHostControl_h.v"

`include "usbHostControl_h.v"

`include "usbConstants_h.v"

`include "usbConstants_h.v"

Line 148...

Line 142...

        next_sendPacketArbiterReq <= 1'b1;

        next_sendPacketArbiterReq <= 1'b1;

end

end

end

end

    `CHK_TYPE:

    `CHK_TYPE:

    begin

    begin

      if (transType == `OUTDATA0_TRANS)

      if (transType == `IN_TRANS)

      begin

        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;

end

      else if (transType == `IN_TRANS)

      begin

      begin

        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;

        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;

end

end

      else if (transType == `SETUP_TRANS)

      else if (transType == `OUTDATA0_TRANS)

      begin

      begin

        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;

        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;

end

end

      else if (transType == `OUTDATA1_TRANS)

      else if (transType == `OUTDATA1_TRANS)

      begin

      begin

        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;

        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;

end

end

      else if (transType == `SETUP_TRANS)

      begin

        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;

end

end

end

    `FLAG:

    `FLAG:

    begin

    begin

      next_transDone <= 1'b1;

      next_transDone <= 1'b1;

      next_clearTXReq <= 1'b1;

      next_clearTXReq <= 1'b1;

Line 306...

Line 300...

        NextState_hstCntrl <= `FLAG;

        NextState_hstCntrl <= `FLAG;

end

end

end

end

    `OUT0_WAIT_DATA0_SENT:

    `OUT0_WAIT_DATA0_SENT:

    begin

    begin

      next_sendPacketWEn <= 1'b0;

      if (sendPacketRdy == 1'b1)

      if (sendPacketRdy == 1'b1)

      begin

      begin

        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;

        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;

        next_getPacketREn <= 1'b1;

        next_getPacketREn <= 1'b1;

end

end

Line 360...

Line 353...

        next_sendPacketPID <= `DATA1;

        next_sendPacketPID <= `DATA1;

end

end

end

end

    `OUT1_WAIT_DATA1_SENT:

    `OUT1_WAIT_DATA1_SENT:

    begin

    begin

      next_sendPacketWEn <= 1'b0;

      if (sendPacketRdy == 1'b1)

      if (sendPacketRdy == 1'b1)

      begin

      begin

        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;

        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;

        next_getPacketREn <= 1'b1;

        next_getPacketREn <= 1'b1;

end

end

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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [hostcontroller.v] - Diff between revs 7 and 9