OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacket.asf] - Diff between revs 9 and 14

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Rev 9 Rev 14
Line 3... Line 3...
FILE="sendpacket.asf"
FILE="sendpacket.asf"
FID=405e9201
FID=405e9201
LANGUAGE=VERILOG
LANGUAGE=VERILOG
ENTITY="sendPacket"
ENTITY="sendPacket"
FRAMES=ON
FRAMES=ON
FREEOID=225
FREEOID=260
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
END
END
BUNDLES
BUNDLES
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B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
Line 52... Line 52...
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PAGE 25400,0 215900,279400
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PAGE 25400,25400 215900,279400
 
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PAGE 25400,25400 215900,279400
 
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OBJECTS
OBJECTS
L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
I 12 6 0 Builtin Reset | 74872,202290
I 12 6 0 Builtin Reset | 74872,202290
Line 71... Line 83...
I 29 25 0 Builtin Exit | 144780,121920
I 29 25 0 Builtin Exit | 144780,121920
I 28 25 0 Builtin Entry | 48013,256695
I 28 25 0 Builtin Entry | 48013,256695
L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
C 23 22 0 TEXT "Conditions" | 114645,116706 1 0 0 "HCTxPortGnt == 1'b1"
C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1"
W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 113134,104869 113443,100466
W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806
S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
Line 121... Line 133...
L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
I 84 51 0 Builtin Entry | 48374,241112
I 84 51 0 Builtin Entry | 48374,241112
I 83 51 0 Builtin Exit | 161275,73621
I 83 51 0 Builtin Exit | 161275,73621
W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
C 81 50 0 TEXT "Conditions" | 136066,86256 1 0 0 "PID == `DATA0 || PID == `DATA1"
C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
Line 207... Line 219...
I 189 0 2 Builtin InPort | 198532,251890 "" ""
I 189 0 2 Builtin InPort | 198532,251890 "" ""
L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
I 195 0 128 Builtin Signal | 35000,231468 "" ""
I 195 0 128 Builtin Signal | 35000,231468 "" ""
L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
I 199 0 130 Builtin InPort | 101972,241240 "" ""
I 199 0 130 Builtin InPort | 101972,241240 "" ""
L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
I 201 0 130 Builtin InPort | 101760,245904 "" ""
I 201 0 130 Builtin InPort | 101760,245904 "" ""
L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
Line 238... Line 250...
A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
 
H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
 
S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
 
L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
 
I 230 229 0 Builtin Entry | 86360,167640
 
I 231 229 0 Builtin Exit | 129540,111760
 
W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
 
L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
 
I 234 0 2 Builtin InPort | 156660,245408 "" ""
 
L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
 
S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
 
W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
 
W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
 
W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
 
                                        202640,35412 197280,23183 191376,19540 185472,15898\
 
                                        167213,13552 158043,13342 148873,13133 131482,15160\
 
                                        122270,15913
 
C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
 
H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
 
S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
 
L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
 
I 250 241 0 Builtin Entry | 60577,248468
 
I 251 241 0 Builtin Exit | 157344,113693
 
W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
 
S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
 
L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
 
W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
 
C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
 
A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
 
A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
 
W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
END
END

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