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Line 46... |
`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
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module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
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input clk;
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input clk;
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input [7:0]fifoData;
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input [7:0]fifoData;
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input fifoEmpty;
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input fifoEmpty;
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input fullSpeedPolarity;
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input HCTxPortGnt;
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input HCTxPortGnt;
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input HCTxPortRdy;
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input HCTxPortRdy;
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input [3:0]PID;
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input [3:0]PID;
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input rst;
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input rst;
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input sendPacketWEn;
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input sendPacketWEn;
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Line 71... |
wire clk;
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wire clk;
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wire [7:0]fifoData;
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wire [7:0]fifoData;
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wire fifoEmpty;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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reg fifoReadEn, next_fifoReadEn;
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reg [10:0]frameNum, next_frameNum;
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reg [10:0]frameNum, next_frameNum;
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wire fullSpeedPolarity;
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reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0]HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0]HCTxPortData, next_HCTxPortData;
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reg [7:0]HCTxPortData, next_HCTxPortData;
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wire HCTxPortGnt;
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wire HCTxPortGnt;
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wire HCTxPortRdy;
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wire HCTxPortRdy;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortReq, next_HCTxPortReq;
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Line 111... |
`define DATA0_DATA1_TERM_BYTE 5'b10000
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`define DATA0_DATA1_TERM_BYTE 5'b10000
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`define OUT_IN_SETUP_CLR_WEN1 5'b10001
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`define OUT_IN_SETUP_CLR_WEN1 5'b10001
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`define SEND_SOF_CLR_WEN1 5'b10010
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`define SEND_SOF_CLR_WEN1 5'b10010
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`define DATA0_DATA1_CLR_WEN 5'b10011
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`define DATA0_DATA1_CLR_WEN 5'b10011
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`define DATA0_DATA1_CLR_REN 5'b10100
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`define DATA0_DATA1_CLR_REN 5'b10100
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`define LS_EOP_WAIT_RDY 5'b10101
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`define LS_EOP_FIN 5'b10110
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reg [4:0]CurrState_sndPkt, NextState_sndPkt;
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reg [4:0]CurrState_sndPkt, NextState_sndPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @(PID)
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always @(PID)
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Line 126... |
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// Machine: sndPkt
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// Machine: sndPkt
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
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always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
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begin
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begin
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NextState_sndPkt <= CurrState_sndPkt;
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NextState_sndPkt <= CurrState_sndPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketRdy <= sendPacketRdy;
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next_sendPacketRdy <= sendPacketRdy;
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next_fifoReadEn <= fifoReadEn;
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next_fifoReadEn <= fifoReadEn;
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next_HCTxPortReq <= 1'b1;
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next_HCTxPortReq <= 1'b1;
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end
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end
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end
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end
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`SP_WAIT_GNT:
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`SP_WAIT_GNT:
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begin
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begin
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if (HCTxPortGnt == 1'b1)
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if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
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begin
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NextState_sndPkt <= `LS_EOP_WAIT_RDY;
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end
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else if (HCTxPortGnt == 1'b1)
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begin
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begin
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NextState_sndPkt <= `SEND_PID_WAIT_RDY;
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NextState_sndPkt <= `SEND_PID_WAIT_RDY;
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end
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end
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end
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end
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`FIN_SP:
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`FIN_SP:
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`DATA0_DATA1_CLR_REN:
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`DATA0_DATA1_CLR_REN:
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begin
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begin
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next_fifoReadEn <= 1'b0;
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next_fifoReadEn <= 1'b0;
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NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
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NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
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end
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end
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`LS_EOP_WAIT_RDY:
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begin
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if (HCTxPortRdy == 1'b1)
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begin
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NextState_sndPkt <= `LS_EOP_FIN;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= 8'h00;
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next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
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end
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end
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`LS_EOP_FIN:
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begin
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next_HCTxPortWEn <= 1'b0;
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NextState_sndPkt <= `FIN_SP;
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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always @ (posedge clk)
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always @ (posedge clk)
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