| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// sendPacket
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// Author :
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//// ////
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// Company :
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacket.v
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// $Id: sendpacket.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
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// Generated : 09/25/04 06:36:27
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// From : c:\projects\USBHostSlave\RTL\hostController\sendpacket.asf
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// By : FSM2VHDL ver. 4.0.5.2
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, rst, sendPacketRdy, sendPacketWEn);
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module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
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input HCTxPortGnt;
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input HCTxPortRdy;
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input [3:0] PID;
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input [6:0] TxAddr;
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input clk;
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input clk;
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input [7:0] fifoData;
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input [7:0] fifoData;
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input fifoEmpty;
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input fifoEmpty;
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input HCTxPortGnt;
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input HCTxPortRdy;
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input [3:0]PID;
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input rst;
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input rst;
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input sendPacketWEn;
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input sendPacketWEn;
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input [6:0]TxAddr;
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input [3:0]TxEndP;
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output fifoReadEn;
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output [10:0]frameNum;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortData;
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output [7:0] HCTxPortData;
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output HCTxPortReq;
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output HCTxPortReq;
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output HCTxPortWEn;
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output HCTxPortWEn;
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output [3:0] TxEndP;
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output fifoReadEn;
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output [10:0] frameNum;
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output sendPacketRdy;
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output sendPacketRdy;
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wire clk;
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wire [7:0]fifoData;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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reg [10:0]frameNum, next_frameNum;
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reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0] HCTxPortData, next_HCTxPortData;
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reg [7:0] HCTxPortData, next_HCTxPortData;
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wire HCTxPortGnt;
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wire HCTxPortGnt;
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wire HCTxPortRdy;
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wire HCTxPortRdy;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortWEn, next_HCTxPortWEn;
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reg HCTxPortWEn, next_HCTxPortWEn;
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wire [3:0] PID;
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wire [3:0] PID;
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wire [6:0] TxAddr;
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reg [3:0] TxEndP, next_TxEndP;
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wire clk;
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wire [7:0] fifoData;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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reg [10:0] frameNum, next_frameNum;
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wire rst;
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wire rst;
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reg sendPacketRdy, next_sendPacketRdy;
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reg sendPacketRdy, next_sendPacketRdy;
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wire sendPacketWEn;
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wire sendPacketWEn;
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wire [6:0]TxAddr;
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wire [3:0]TxEndP;
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// diagram signals declarations
|
// diagram signals declarations
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reg [7:0]PIDNotPID;
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reg [7:0]PIDNotPID;
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// BINARY ENCODED state machine: sndPkt
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// BINARY ENCODED state machine: sndPkt
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| Line 86... |
Line 116... |
`define OUT_IN_SETUP_CLR_WEN1 5'b10001
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`define OUT_IN_SETUP_CLR_WEN1 5'b10001
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`define SEND_SOF_CLR_WEN1 5'b10010
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`define SEND_SOF_CLR_WEN1 5'b10010
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`define DATA0_DATA1_CLR_WEN 5'b10011
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`define DATA0_DATA1_CLR_WEN 5'b10011
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`define DATA0_DATA1_CLR_REN 5'b10100
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`define DATA0_DATA1_CLR_REN 5'b10100
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reg [4:0] CurrState_sndPkt;
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reg [4:0]CurrState_sndPkt, NextState_sndPkt;
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reg [4:0] NextState_sndPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @(PID)
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always @(PID)
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begin
|
begin
|
PIDNotPID <= { (PID ^ 4'hf), PID };
|
PIDNotPID <= { (PID ^ 4'hf), PID };
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end
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end
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//--------------------------------------------------------------------
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// Machine: sndPkt
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// Machine: sndPkt
|
//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
//----------------------------------
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always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
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always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PID or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
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begin
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begin : sndPkt_NextState
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NextState_sndPkt <= CurrState_sndPkt;
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NextState_sndPkt <= CurrState_sndPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketRdy <= sendPacketRdy;
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next_sendPacketRdy <= sendPacketRdy;
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next_HCTxPortReq <= HCTxPortReq;
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next_fifoReadEn <= fifoReadEn;
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortCntl <= HCTxPortCntl;
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next_HCTxPortCntl <= HCTxPortCntl;
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortReq <= HCTxPortReq;
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next_frameNum <= frameNum;
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next_frameNum <= frameNum;
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next_fifoReadEn <= fifoReadEn;
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case (CurrState_sndPkt) // synopsys parallel_case full_case
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case (CurrState_sndPkt) // synopsys parallel_case full_case
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`START_SP:
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`START_SP:
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|
begin
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NextState_sndPkt <= `WAIT_ENABLE;
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NextState_sndPkt <= `WAIT_ENABLE;
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end
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`WAIT_ENABLE:
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`WAIT_ENABLE:
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begin
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if (sendPacketWEn == 1'b1)
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if (sendPacketWEn == 1'b1)
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begin
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begin
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NextState_sndPkt <= `SP_WAIT_GNT;
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NextState_sndPkt <= `SP_WAIT_GNT;
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next_sendPacketRdy <= 1'b0;
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next_sendPacketRdy <= 1'b0;
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next_HCTxPortReq <= 1'b1;
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next_HCTxPortReq <= 1'b1;
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end
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end
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end
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`SP_WAIT_GNT:
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`SP_WAIT_GNT:
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begin
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if (HCTxPortGnt == 1'b1)
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if (HCTxPortGnt == 1'b1)
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begin
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NextState_sndPkt <= `SEND_PID_WAIT_RDY;
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NextState_sndPkt <= `SEND_PID_WAIT_RDY;
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end
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end
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`FIN_SP:
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`FIN_SP:
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begin
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begin
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NextState_sndPkt <= `WAIT_ENABLE;
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NextState_sndPkt <= `WAIT_ENABLE;
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next_sendPacketRdy <= 1'b1;
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next_sendPacketRdy <= 1'b1;
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next_HCTxPortReq <= 1'b0;
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next_HCTxPortReq <= 1'b0;
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end
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end
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`SEND_PID_WAIT_RDY:
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`SEND_PID_WAIT_RDY:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
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begin
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begin
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NextState_sndPkt <= `SEND_PID_FIN;
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NextState_sndPkt <= `SEND_PID_FIN;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= PIDNotPID;
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next_HCTxPortData <= PIDNotPID;
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next_HCTxPortCntl <= `TX_PACKET_START;
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next_HCTxPortCntl <= `TX_PACKET_START;
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end
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end
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end
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`SEND_PID_FIN:
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`SEND_PID_FIN:
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begin
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begin
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next_HCTxPortWEn <= 1'b0;
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next_HCTxPortWEn <= 1'b0;
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if (PID == `DATA0 || PID == `DATA1)
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if (PID == `DATA0 || PID == `DATA1)
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begin
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NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
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NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
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end
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else if (PID == `SOF)
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else if (PID == `SOF)
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begin
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NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
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NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
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end
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else if (PID == `OUT ||
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else if (PID == `OUT ||
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PID == `IN ||
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PID == `IN ||
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PID == `SETUP)
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PID == `SETUP)
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begin
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NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
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NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
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end
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else
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else
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begin
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NextState_sndPkt <= `FIN_SP;
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NextState_sndPkt <= `FIN_SP;
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end
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end
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end
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`OUT_IN_SETUP_WAIT_RDY1:
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`OUT_IN_SETUP_WAIT_RDY1:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
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begin
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begin
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NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
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NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
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next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
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next_HCTxPortCntl <= `TX_PACKET_STREAM;
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next_HCTxPortCntl <= `TX_PACKET_STREAM;
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end
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end
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end
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`OUT_IN_SETUP_WAIT_RDY2:
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`OUT_IN_SETUP_WAIT_RDY2:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_sndPkt <= `OUT_IN_SETUP_FIN;
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NextState_sndPkt <= `OUT_IN_SETUP_FIN;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
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next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
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next_HCTxPortCntl <= `TX_PACKET_STREAM;
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next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
end
|
end
|
|
end
|
`OUT_IN_SETUP_FIN:
|
`OUT_IN_SETUP_FIN:
|
begin
|
begin
|
next_HCTxPortWEn <= 1'b0;
|
next_HCTxPortWEn <= 1'b0;
|
NextState_sndPkt <= `FIN_SP;
|
NextState_sndPkt <= `FIN_SP;
|
end
|
end
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| Line 187... |
Line 235... |
next_HCTxPortWEn <= 1'b0;
|
next_HCTxPortWEn <= 1'b0;
|
next_frameNum <= frameNum + 1'b1;
|
next_frameNum <= frameNum + 1'b1;
|
NextState_sndPkt <= `FIN_SP;
|
NextState_sndPkt <= `FIN_SP;
|
end
|
end
|
`SEND_SOF_WAIT_RDY3:
|
`SEND_SOF_WAIT_RDY3:
|
|
begin
|
if (HCTxPortRdy == 1'b1)
|
if (HCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
|
NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortData <= frameNum[7:0];
|
next_HCTxPortData <= frameNum[7:0];
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
end
|
end
|
|
end
|
`SEND_SOF_WAIT_RDY4:
|
`SEND_SOF_WAIT_RDY4:
|
|
begin
|
if (HCTxPortRdy == 1'b1)
|
if (HCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_sndPkt <= `SEND_SOF_FIN1;
|
NextState_sndPkt <= `SEND_SOF_FIN1;
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortData <= {5'b00000, frameNum[10:8]};
|
next_HCTxPortData <= {5'b00000, frameNum[10:8]};
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
end
|
end
|
|
end
|
`SEND_SOF_CLR_WEN1:
|
`SEND_SOF_CLR_WEN1:
|
begin
|
begin
|
next_HCTxPortWEn <= 1'b0;
|
next_HCTxPortWEn <= 1'b0;
|
NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
|
NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
|
end
|
end
|
| Line 215... |
Line 267... |
next_HCTxPortData <= fifoData;
|
next_HCTxPortData <= fifoData;
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
next_HCTxPortCntl <= `TX_PACKET_STREAM;
|
NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
|
NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
|
end
|
end
|
`DATA0_DATA1_WAIT_READ_FIFO:
|
`DATA0_DATA1_WAIT_READ_FIFO:
|
|
begin
|
if (HCTxPortRdy == 1'b1)
|
if (HCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
|
NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
|
next_fifoReadEn <= 1'b1;
|
next_fifoReadEn <= 1'b1;
|
end
|
end
|
|
end
|
`DATA0_DATA1_FIFO_EMPTY:
|
`DATA0_DATA1_FIFO_EMPTY:
|
|
begin
|
if (fifoEmpty == 1'b0)
|
if (fifoEmpty == 1'b0)
|
|
begin
|
NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
|
NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
|
|
end
|
else
|
else
|
|
begin
|
NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
|
NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
|
|
end
|
|
end
|
`DATA0_DATA1_FIN:
|
`DATA0_DATA1_FIN:
|
begin
|
begin
|
next_HCTxPortWEn <= 1'b0;
|
next_HCTxPortWEn <= 1'b0;
|
NextState_sndPkt <= `FIN_SP;
|
NextState_sndPkt <= `FIN_SP;
|
end
|
end
|
`DATA0_DATA1_TERM_BYTE:
|
`DATA0_DATA1_TERM_BYTE:
|
|
begin
|
if (HCTxPortRdy == 1'b1)
|
if (HCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_sndPkt <= `DATA0_DATA1_FIN;
|
NextState_sndPkt <= `DATA0_DATA1_FIN;
|
//Last byte is not valid data,
|
//Last byte is not valid data,
|
//but the 'TX_PACKET_STOP' flag is required
|
//but the 'TX_PACKET_STOP' flag is required
|
//by the SIE state machine to detect end of data packet
|
//by the SIE state machine to detect end of data packet
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortWEn <= 1'b1;
|
next_HCTxPortData <= 8'h00;
|
next_HCTxPortData <= 8'h00;
|
next_HCTxPortCntl <= `TX_PACKET_STOP;
|
next_HCTxPortCntl <= `TX_PACKET_STOP;
|
end
|
end
|
|
end
|
`DATA0_DATA1_CLR_WEN:
|
`DATA0_DATA1_CLR_WEN:
|
begin
|
begin
|
next_HCTxPortWEn <= 1'b0;
|
next_HCTxPortWEn <= 1'b0;
|
NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
|
NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
|
end
|
end
|
| Line 254... |
Line 316... |
NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
|
NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : sndPkt_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_sndPkt <= `START_SP;
|
CurrState_sndPkt <= `START_SP;
|
else
|
else
|
CurrState_sndPkt <= NextState_sndPkt;
|
CurrState_sndPkt <= NextState_sndPkt;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : sndPkt_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
sendPacketRdy <= 1'b1;
|
sendPacketRdy <= 1'b1;
|
HCTxPortReq <= 1'b0;
|
fifoReadEn <= 1'b0;
|
HCTxPortWEn <= 1'b0;
|
|
HCTxPortData <= 8'h00;
|
HCTxPortData <= 8'h00;
|
HCTxPortCntl <= 8'h00;
|
HCTxPortCntl <= 8'h00;
|
|
HCTxPortWEn <= 1'b0;
|
|
HCTxPortReq <= 1'b0;
|
frameNum <= 11'h000;
|
frameNum <= 11'h000;
|
fifoReadEn <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sendPacketRdy <= next_sendPacketRdy;
|
sendPacketRdy <= next_sendPacketRdy;
|
HCTxPortReq <= next_HCTxPortReq;
|
fifoReadEn <= next_fifoReadEn;
|
HCTxPortWEn <= next_HCTxPortWEn;
|
|
HCTxPortData <= next_HCTxPortData;
|
HCTxPortData <= next_HCTxPortData;
|
HCTxPortCntl <= next_HCTxPortCntl;
|
HCTxPortCntl <= next_HCTxPortCntl;
|
|
HCTxPortWEn <= next_HCTxPortWEn;
|
|
HCTxPortReq <= next_HCTxPortReq;
|
frameNum <= next_frameNum;
|
frameNum <= next_frameNum;
|
fifoReadEn <= next_fifoReadEn;
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
|
