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//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// sendpacketarbiter
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// Author :
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//// ////
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// Company :
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketarbiter.v
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// $Id: sendpacketarbiter.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
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// Generated : 09/10/04 20:20:24
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// From : c:\projects\USBHostSlave\RTL\hostController\sendpacketarbiter.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
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module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
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input HCTxReq;
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input clk;
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input [3:0] HC_PID;
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input [3:0] HC_PID;
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input HC_SP_WEn;
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input HC_SP_WEn;
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input SOFTxReq;
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input HCTxReq;
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input SOF_SP_WEn;
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input clk;
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input rst;
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input rst;
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input SOF_SP_WEn;
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input SOFTxReq;
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output HCTxGnt;
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output HCTxGnt;
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output SOFTxGnt;
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output [3:0] sendPacketPID;
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output [3:0] sendPacketPID;
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output sendPacketWEnable;
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output sendPacketWEnable;
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output SOFTxGnt;
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reg HCTxGnt, next_HCTxGnt;
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wire clk;
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wire HCTxReq;
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wire [3:0] HC_PID;
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wire [3:0] HC_PID;
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wire HC_SP_WEn;
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wire HC_SP_WEn;
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reg SOFTxGnt, next_SOFTxGnt;
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reg HCTxGnt, next_HCTxGnt;
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wire SOFTxReq;
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wire HCTxReq;
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wire SOF_SP_WEn;
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wire clk;
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wire rst;
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wire rst;
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reg [3:0] sendPacketPID, next_sendPacketPID;
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reg [3:0] sendPacketPID, next_sendPacketPID;
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reg sendPacketWEnable, next_sendPacketWEnable;
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reg sendPacketWEnable, next_sendPacketWEnable;
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wire SOF_SP_WEn;
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reg SOFTxGnt, next_SOFTxGnt;
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wire SOFTxReq;
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// diagram signals declarations
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// diagram signals declarations
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reg muxSOFNotHC, next_muxSOFNotHC;
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reg muxSOFNotHC, next_muxSOFNotHC;
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// BINARY ENCODED state machine: sendPktArb
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// BINARY ENCODED state machine: sendPktArb
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`define HC_ACT 2'b00
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`define HC_ACT 2'b00
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`define SOF_ACT 2'b01
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`define SOF_ACT 2'b01
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`define SARB_WAIT_REQ 2'b10
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`define SARB_WAIT_REQ 2'b10
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`define START_SARB 2'b11
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`define START_SARB 2'b11
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reg [1:0] CurrState_sendPktArb;
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reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
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reg [1:0] NextState_sendPktArb;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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// hostController/SOFTransmit mux
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// hostController/SOFTransmit mux
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always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
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always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
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begin
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begin
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sendPacketPID <= HC_PID;
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sendPacketPID <= HC_PID;
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end
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end
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end
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end
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//--------------------------------------------------------------------
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// Machine: sendPktArb
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// Machine: sendPktArb
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
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always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
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begin : sendPktArb_NextState
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begin
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NextState_sendPktArb <= CurrState_sendPktArb;
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NextState_sendPktArb <= CurrState_sendPktArb;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_HCTxGnt <= HCTxGnt;
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next_HCTxGnt <= HCTxGnt;
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next_SOFTxGnt <= SOFTxGnt;
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next_SOFTxGnt <= SOFTxGnt;
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next_muxSOFNotHC <= muxSOFNotHC;
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next_muxSOFNotHC <= muxSOFNotHC;
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case (CurrState_sendPktArb) // synopsys parallel_case full_case
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case (CurrState_sendPktArb) // synopsys parallel_case full_case
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`HC_ACT:
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`HC_ACT:
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begin
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if (HCTxReq == 1'b0)
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if (HCTxReq == 1'b0)
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begin
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begin
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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next_HCTxGnt <= 1'b0;
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next_HCTxGnt <= 1'b0;
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end
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end
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end
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`SOF_ACT:
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`SOF_ACT:
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begin
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if (SOFTxReq == 1'b0)
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if (SOFTxReq == 1'b0)
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begin
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begin
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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next_SOFTxGnt <= 1'b0;
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next_SOFTxGnt <= 1'b0;
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end
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end
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end
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`SARB_WAIT_REQ:
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`SARB_WAIT_REQ:
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begin
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if (SOFTxReq == 1'b1)
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if (SOFTxReq == 1'b1)
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begin
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begin
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NextState_sendPktArb <= `SOF_ACT;
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NextState_sendPktArb <= `SOF_ACT;
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next_SOFTxGnt <= 1'b1;
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next_SOFTxGnt <= 1'b1;
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next_muxSOFNotHC <= 1'b1;
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next_muxSOFNotHC <= 1'b1;
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begin
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begin
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NextState_sendPktArb <= `HC_ACT;
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NextState_sendPktArb <= `HC_ACT;
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next_HCTxGnt <= 1'b1;
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next_HCTxGnt <= 1'b1;
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next_muxSOFNotHC <= 1'b0;
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next_muxSOFNotHC <= 1'b0;
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end
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end
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end
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`START_SARB:
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`START_SARB:
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begin
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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NextState_sendPktArb <= `SARB_WAIT_REQ;
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : sendPktArb_CurrentState
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begin
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if (rst)
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if (rst)
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CurrState_sendPktArb <= `START_SARB;
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CurrState_sendPktArb <= `START_SARB;
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else
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else
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CurrState_sendPktArb <= NextState_sendPktArb;
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CurrState_sendPktArb <= NextState_sendPktArb;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : sendPktArb_RegOutput
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begin
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if (rst)
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if (rst)
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begin
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begin
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muxSOFNotHC <= 1'b0;
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SOFTxGnt <= 1'b0;
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HCTxGnt <= 1'b0;
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HCTxGnt <= 1'b0;
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SOFTxGnt <= 1'b0;
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muxSOFNotHC <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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muxSOFNotHC <= next_muxSOFNotHC;
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SOFTxGnt <= next_SOFTxGnt;
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HCTxGnt <= next_HCTxGnt;
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HCTxGnt <= next_HCTxGnt;
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SOFTxGnt <= next_SOFTxGnt;
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muxSOFNotHC <= next_muxSOFNotHC;
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end
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end
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end
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end
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endmodule
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endmodule
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