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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
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module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
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input clk;
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input clk;
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input preAmbleEnable;
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input preAmbleEnable;
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input rst;
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input rst;
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input [3:0]sendPacketCPPID;
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input [3:0]sendPacketCPPID;
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input sendPacketCPWEn;
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input sendPacketCPWEn;
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input sendPacketRdy;
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input sendPacketRdy;
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output fullSpeedBitRate;
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output fullSpeedPolarity;
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output grabLineControl; // mux select
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output sendPacketCPReady;
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output sendPacketCPReady;
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output [3:0]sendPacketPID;
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output [3:0]sendPacketPID;
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output sendPacketWEn;
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output sendPacketWEn;
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wire clk;
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wire clk;
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reg fullSpeedBitRate, next_fullSpeedBitRate;
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reg fullSpeedPolarity, next_fullSpeedPolarity;
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reg grabLineControl, next_grabLineControl;
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wire preAmbleEnable;
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wire preAmbleEnable;
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wire rst;
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wire rst;
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wire [3:0]sendPacketCPPID;
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wire [3:0]sendPacketCPPID;
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reg sendPacketCPReady, next_sendPacketCPReady;
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reg sendPacketCPReady, next_sendPacketCPReady;
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wire sendPacketCPWEn;
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wire sendPacketCPWEn;
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Line 71... |
`define SPC_WAIT_EN 4'b0000
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`define SPC_WAIT_EN 4'b0000
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`define START_SPC 4'b0001
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`define START_SPC 4'b0001
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`define CHK_PREAM 4'b0010
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`define CHK_PREAM 4'b0010
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`define PREAM_PKT_SND_PREAM 4'b0011
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`define PREAM_PKT_SND_PREAM 4'b0011
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`define PREAM_PKT_WAIT_RDY1 4'b0100
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`define PREAM_PKT_WAIT_RDY1 4'b0100
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`define PREAM_PKT_WAIT_RDY2 4'b0101
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`define PREAM_PKT_PREAM_SENT 4'b0101
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`define PREAM_PKT_SND_PID 4'b0110
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`define PREAM_PKT_SND_PID 4'b0110
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`define PREAM_PKT_WAIT_RDY3 4'b0111
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`define PREAM_PKT_PID_SENT 4'b0111
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`define REG_PKT_SEND_PID 4'b1000
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`define REG_PKT_SEND_PID 4'b1000
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`define REG_PKT_WAIT_RDY1 4'b1001
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`define REG_PKT_WAIT_RDY1 4'b1001
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`define REG_PKT_WAIT_RDY 4'b1010
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`define REG_PKT_WAIT_RDY 4'b1010
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`define READY 4'b1011
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`define READY 4'b1011
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`define PREAM_PKT_WAIT_RDY2 4'b1100
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`define PREAM_PKT_WAIT_RDY3 4'b1101
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reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
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reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
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// Machine: sendPktCP
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// Machine: sendPktCP
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
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always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
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begin
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begin
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NextState_sendPktCP <= CurrState_sendPktCP;
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NextState_sendPktCP <= CurrState_sendPktCP;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketCPReady <= sendPacketCPReady;
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next_sendPacketCPReady <= sendPacketCPReady;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketPID <= sendPacketPID;
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next_fullSpeedBitRate <= fullSpeedBitRate;
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next_fullSpeedPolarity <= fullSpeedPolarity;
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next_grabLineControl <= grabLineControl;
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case (CurrState_sendPktCP) // synopsys parallel_case full_case
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case (CurrState_sendPktCP) // synopsys parallel_case full_case
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`SPC_WAIT_EN:
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`SPC_WAIT_EN:
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begin
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begin
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if (sendPacketCPWEn == 1'b1)
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if (sendPacketCPWEn == 1'b1)
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begin
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begin
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Line 127... |
end
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end
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`PREAM_PKT_SND_PREAM:
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`PREAM_PKT_SND_PREAM:
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begin
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begin
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `PREAMBLE;
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next_sendPacketPID <= `PREAMBLE;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
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NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
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next_sendPacketWEn <= 1'b0;
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end
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end
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`PREAM_PKT_WAIT_RDY1:
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`PREAM_PKT_WAIT_RDY1:
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begin
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
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NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
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next_fullSpeedBitRate <= 1'b1;
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next_fullSpeedPolarity <= 1'b1;
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next_grabLineControl <= 1'b1;
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end
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end
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end
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end
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`PREAM_PKT_WAIT_RDY2:
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`PREAM_PKT_PREAM_SENT:
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begin
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_sendPktCP <= `PREAM_PKT_SND_PID;
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next_sendPacketWEn <= 1'b0;
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next_fullSpeedBitRate <= 1'b1;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
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end
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end
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end
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`PREAM_PKT_SND_PID:
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`PREAM_PKT_SND_PID:
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begin
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begin
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= sendPacketCPPID;
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next_sendPacketPID <= sendPacketCPPID;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
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NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
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end
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`PREAM_PKT_PID_SENT:
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
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end
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`PREAM_PKT_WAIT_RDY2:
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begin
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if (sendPacketRdy == 1'b1)
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begin
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NextState_sendPktCP <= `PREAM_PKT_SND_PID;
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end
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end
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end
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`PREAM_PKT_WAIT_RDY3:
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`PREAM_PKT_WAIT_RDY3:
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begin
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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begin
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NextState_sendPktCP <= `READY;
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NextState_sendPktCP <= `READY;
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next_grabLineControl <= 1'b0;
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end
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end
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end
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end
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`REG_PKT_SEND_PID:
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`REG_PKT_SEND_PID:
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begin
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begin
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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if (rst)
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if (rst)
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begin
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begin
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sendPacketCPReady <= 1'b1;
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sendPacketCPReady <= 1'b1;
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sendPacketWEn <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketPID <= 4'b0;
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sendPacketPID <= 4'b0;
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fullSpeedBitRate <= 1'b0;
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fullSpeedPolarity <= 1'b0;
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grabLineControl <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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sendPacketCPReady <= next_sendPacketCPReady;
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sendPacketCPReady <= next_sendPacketCPReady;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketPID <= next_sendPacketPID;
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sendPacketPID <= next_sendPacketPID;
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fullSpeedBitRate <= next_fullSpeedBitRate;
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fullSpeedPolarity <= next_fullSpeedPolarity;
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grabLineControl <= next_grabLineControl;
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end
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end
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end
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end
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endmodule
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endmodule
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