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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Diff between revs 9 and 14

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Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`include "usbConstants_h.v"
`include "usbConstants_h.v"
 
 
module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
input   clk;
input   clk;
input   preAmbleEnable;
input   preAmbleEnable;
input   rst;
input   rst;
input   [3:0]sendPacketCPPID;
input   [3:0]sendPacketCPPID;
input   sendPacketCPWEn;
input   sendPacketCPWEn;
input   sendPacketRdy;
input   sendPacketRdy;
output  fullSpeedBitRate;
 
output  fullSpeedPolarity;
 
output  grabLineControl;    // mux select
 
output  sendPacketCPReady;
output  sendPacketCPReady;
output  [3:0]sendPacketPID;
output  [3:0]sendPacketPID;
output  sendPacketWEn;
output  sendPacketWEn;
 
 
wire    clk;
wire    clk;
reg     fullSpeedBitRate, next_fullSpeedBitRate;
 
reg     fullSpeedPolarity, next_fullSpeedPolarity;
 
reg     grabLineControl, next_grabLineControl;
 
wire    preAmbleEnable;
wire    preAmbleEnable;
wire    rst;
wire    rst;
wire    [3:0]sendPacketCPPID;
wire    [3:0]sendPacketCPPID;
reg     sendPacketCPReady, next_sendPacketCPReady;
reg     sendPacketCPReady, next_sendPacketCPReady;
wire    sendPacketCPWEn;
wire    sendPacketCPWEn;
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`define SPC_WAIT_EN 4'b0000
`define SPC_WAIT_EN 4'b0000
`define START_SPC 4'b0001
`define START_SPC 4'b0001
`define CHK_PREAM 4'b0010
`define CHK_PREAM 4'b0010
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_SND_PREAM 4'b0011
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_WAIT_RDY1 4'b0100
`define PREAM_PKT_WAIT_RDY2 4'b0101
`define PREAM_PKT_PREAM_SENT 4'b0101
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_SND_PID 4'b0110
`define PREAM_PKT_WAIT_RDY3 4'b0111
`define PREAM_PKT_PID_SENT 4'b0111
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_SEND_PID 4'b1000
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY1 4'b1001
`define REG_PKT_WAIT_RDY 4'b1010
`define REG_PKT_WAIT_RDY 4'b1010
`define READY 4'b1011
`define READY 4'b1011
 
`define PREAM_PKT_WAIT_RDY2 4'b1100
 
`define PREAM_PKT_WAIT_RDY3 4'b1101
 
 
reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
 
 
 
 
// Machine: sendPktCP
// Machine: sendPktCP
 
 
// NextState logic (combinatorial)
// NextState logic (combinatorial)
always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
begin
begin
  NextState_sendPktCP <= CurrState_sendPktCP;
  NextState_sendPktCP <= CurrState_sendPktCP;
  // Set default values for outputs and signals
  // Set default values for outputs and signals
  next_sendPacketCPReady <= sendPacketCPReady;
  next_sendPacketCPReady <= sendPacketCPReady;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_sendPacketPID <= sendPacketPID;
  next_fullSpeedBitRate <= fullSpeedBitRate;
 
  next_fullSpeedPolarity <= fullSpeedPolarity;
 
  next_grabLineControl <= grabLineControl;
 
  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
    `SPC_WAIT_EN:
    `SPC_WAIT_EN:
    begin
    begin
      if (sendPacketCPWEn == 1'b1)
      if (sendPacketCPWEn == 1'b1)
      begin
      begin
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    end
    end
    `PREAM_PKT_SND_PREAM:
    `PREAM_PKT_SND_PREAM:
    begin
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= `PREAMBLE;
      next_sendPacketPID <= `PREAMBLE;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
      next_sendPacketWEn <= 1'b0;
 
    end
    end
    `PREAM_PKT_WAIT_RDY1:
    `PREAM_PKT_WAIT_RDY1:
    begin
    begin
      if (sendPacketRdy == 1'b1)
      if (sendPacketRdy == 1'b1)
      begin
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
        next_fullSpeedBitRate <= 1'b1;
 
        next_fullSpeedPolarity <= 1'b1;
 
        next_grabLineControl <= 1'b1;
 
      end
      end
    end
    end
    `PREAM_PKT_WAIT_RDY2:
    `PREAM_PKT_PREAM_SENT:
    begin
 
      if (sendPacketRdy == 1'b1)
 
      begin
      begin
        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
      next_sendPacketWEn <= 1'b0;
        next_fullSpeedBitRate <= 1'b1;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
      end
 
    end
    end
    `PREAM_PKT_SND_PID:
    `PREAM_PKT_SND_PID:
    begin
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketWEn <= 1'b1;
      next_sendPacketPID <= sendPacketCPPID;
      next_sendPacketPID <= sendPacketCPPID;
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
 
    end
 
    `PREAM_PKT_PID_SENT:
 
    begin
      next_sendPacketWEn <= 1'b0;
      next_sendPacketWEn <= 1'b0;
 
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
 
    end
 
    `PREAM_PKT_WAIT_RDY2:
 
    begin
 
      if (sendPacketRdy == 1'b1)
 
      begin
 
        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
 
      end
    end
    end
    `PREAM_PKT_WAIT_RDY3:
    `PREAM_PKT_WAIT_RDY3:
    begin
    begin
      if (sendPacketRdy == 1'b1)
      if (sendPacketRdy == 1'b1)
      begin
      begin
        NextState_sendPktCP <= `READY;
        NextState_sendPktCP <= `READY;
        next_grabLineControl <= 1'b0;
 
      end
      end
    end
    end
    `REG_PKT_SEND_PID:
    `REG_PKT_SEND_PID:
    begin
    begin
      next_sendPacketWEn <= 1'b1;
      next_sendPacketWEn <= 1'b1;
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  if (rst)
  if (rst)
  begin
  begin
    sendPacketCPReady <= 1'b1;
    sendPacketCPReady <= 1'b1;
    sendPacketWEn <= 1'b0;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
    sendPacketPID <= 4'b0;
    fullSpeedBitRate <= 1'b0;
 
    fullSpeedPolarity <= 1'b0;
 
    grabLineControl <= 1'b0;
 
  end
  end
  else
  else
  begin
  begin
    sendPacketCPReady <= next_sendPacketCPReady;
    sendPacketCPReady <= next_sendPacketCPReady;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
    sendPacketPID <= next_sendPacketPID;
    fullSpeedBitRate <= next_fullSpeedBitRate;
 
    fullSpeedPolarity <= next_fullSpeedPolarity;
 
    grabLineControl <= next_grabLineControl;
 
  end
  end
end
end
 
 
endmodule
endmodule
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