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// File : ../RTL/hostController/sendpacketcheckpreamble.v
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// Generated : 10/06/06 19:35:27
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// From : ../RTL/hostController/sendpacketcheckpreamble.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// sendpacketcheckpreamble
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//// sendpacketcheckpreamble
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
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module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
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input clk;
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input clk;
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input preAmbleEnable;
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input preAmbleEnable;
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`define REG_PKT_WAIT_RDY 4'b1010
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`define REG_PKT_WAIT_RDY 4'b1010
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`define READY 4'b1011
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`define READY 4'b1011
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`define PREAM_PKT_WAIT_RDY2 4'b1100
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`define PREAM_PKT_WAIT_RDY2 4'b1100
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`define PREAM_PKT_WAIT_RDY3 4'b1101
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`define PREAM_PKT_WAIT_RDY3 4'b1101
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reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
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reg [3:0] CurrState_sendPktCP;
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reg [3:0] NextState_sendPktCP;
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//--------------------------------------------------------------------
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// Machine: sendPktCP
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// Machine: sendPktCP
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
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begin : sendPktCP_NextState
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NextState_sendPktCP <= CurrState_sendPktCP;
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NextState_sendPktCP <= CurrState_sendPktCP;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketCPReady <= sendPacketCPReady;
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next_sendPacketCPReady <= sendPacketCPReady;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketPID <= sendPacketPID;
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next_sendPacketPID <= sendPacketPID;
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case (CurrState_sendPktCP) // synopsys parallel_case full_case
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case (CurrState_sendPktCP)
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`SPC_WAIT_EN:
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`SPC_WAIT_EN:
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begin
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if (sendPacketCPWEn == 1'b1)
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if (sendPacketCPWEn == 1'b1)
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begin
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begin
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NextState_sendPktCP <= `CHK_PREAM;
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NextState_sendPktCP <= `CHK_PREAM;
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next_sendPacketCPReady <= 1'b0;
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next_sendPacketCPReady <= 1'b0;
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end
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end
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end
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`START_SPC:
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`START_SPC:
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begin
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NextState_sendPktCP <= `SPC_WAIT_EN;
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NextState_sendPktCP <= `SPC_WAIT_EN;
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end
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`CHK_PREAM:
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`CHK_PREAM:
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begin
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if (preAmbleEnable == 1'b1)
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if (preAmbleEnable == 1'b1)
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begin
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
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end
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else
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else
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begin
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NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
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NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
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end
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end
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`READY:
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`READY:
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begin
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begin
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next_sendPacketCPReady <= 1'b1;
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next_sendPacketCPReady <= 1'b1;
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NextState_sendPktCP <= `SPC_WAIT_EN;
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NextState_sendPktCP <= `SPC_WAIT_EN;
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end
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end
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= `PREAMBLE;
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next_sendPacketPID <= `PREAMBLE;
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NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
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NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
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end
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end
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`PREAM_PKT_WAIT_RDY1:
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`PREAM_PKT_WAIT_RDY1:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
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NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
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end
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end
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`PREAM_PKT_PREAM_SENT:
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`PREAM_PKT_PREAM_SENT:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
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end
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end
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
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NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
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end
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end
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`PREAM_PKT_WAIT_RDY2:
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`PREAM_PKT_WAIT_RDY2:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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NextState_sendPktCP <= `PREAM_PKT_SND_PID;
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NextState_sendPktCP <= `PREAM_PKT_SND_PID;
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end
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end
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`PREAM_PKT_WAIT_RDY3:
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`PREAM_PKT_WAIT_RDY3:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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NextState_sendPktCP <= `READY;
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NextState_sendPktCP <= `READY;
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end
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end
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`REG_PKT_SEND_PID:
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`REG_PKT_SEND_PID:
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begin
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begin
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketPID <= sendPacketCPPID;
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next_sendPacketPID <= sendPacketCPPID;
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NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
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NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
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end
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end
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`REG_PKT_WAIT_RDY1:
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`REG_PKT_WAIT_RDY1:
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begin
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if (sendPacketRdy == 1'b1)
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if (sendPacketRdy == 1'b1)
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begin
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NextState_sendPktCP <= `REG_PKT_SEND_PID;
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NextState_sendPktCP <= `REG_PKT_SEND_PID;
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end
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end
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`REG_PKT_WAIT_RDY:
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`REG_PKT_WAIT_RDY:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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NextState_sendPktCP <= `READY;
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NextState_sendPktCP <= `READY;
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : sendPktCP_CurrentState
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if (rst)
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if (rst)
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CurrState_sendPktCP <= `START_SPC;
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CurrState_sendPktCP <= `START_SPC;
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else
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else
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CurrState_sendPktCP <= NextState_sendPktCP;
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CurrState_sendPktCP <= NextState_sendPktCP;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : sendPktCP_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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sendPacketCPReady <= 1'b1;
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sendPacketWEn <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketPID <= 4'b0;
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sendPacketPID <= 4'b0;
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sendPacketCPReady <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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sendPacketCPReady <= next_sendPacketCPReady;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketPID <= next_sendPacketPID;
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sendPacketPID <= next_sendPacketPID;
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sendPacketCPReady <= next_sendPacketCPReady;
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end
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end
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end
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end
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endmodule
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endmodule
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