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//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// sofcontroller
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v
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// $Id: sofcontroller.v,v 1.2 2004-12-18 14:36:11 sfielding Exp $
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// Generated : 09/08/04 06:24:36
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// From : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);
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module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
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input clk;
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input HCTxPortGnt;
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input HCTxPortGnt;
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input HCTxPortRdy;
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input HCTxPortRdy;
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input rst;
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input SOFEnable;
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input SOFEnable;
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input SOFTimerClr;
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input SOFTimerClr;
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input clk;
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input rst;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortCntl;
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output [7:0] HCTxPortData;
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output [7:0] HCTxPortData;
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output HCTxPortReq;
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output HCTxPortReq;
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output HCTxPortWEn;
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output HCTxPortWEn;
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output [15:0] SOFTimer;
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output [15:0] SOFTimer;
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wire clk;
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reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg [7:0] HCTxPortData, next_HCTxPortData;
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reg [7:0] HCTxPortData, next_HCTxPortData;
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wire HCTxPortGnt;
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wire HCTxPortGnt;
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wire HCTxPortRdy;
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wire HCTxPortRdy;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortReq, next_HCTxPortReq;
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reg HCTxPortWEn, next_HCTxPortWEn;
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reg HCTxPortWEn, next_HCTxPortWEn;
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wire rst;
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wire SOFEnable;
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wire SOFEnable;
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wire SOFTimerClr;
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reg [15:0] SOFTimer, next_SOFTimer;
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reg [15:0] SOFTimer, next_SOFTimer;
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wire clk;
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wire SOFTimerClr;
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wire rst;
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// BINARY ENCODED state machine: sofCntl
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// BINARY ENCODED state machine: sofCntl
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// State codes definitions:
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// State codes definitions:
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`define START_SC 3'b000
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`define START_SC 3'b000
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`define WAIT_SOF_EN 3'b001
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`define WAIT_SOF_EN 3'b001
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`define WAIT_SEND_RESUME 3'b010
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`define WAIT_SEND_RESUME 3'b010
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`define INC_TIMER 3'b011
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`define INC_TIMER 3'b011
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`define SC_WAIT_GNT 3'b100
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`define SC_WAIT_GNT 3'b100
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`define CLR_WEN 3'b101
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`define CLR_WEN 3'b101
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reg [2:0] CurrState_sofCntl;
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reg [2:0]CurrState_sofCntl, NextState_sofCntl;
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reg [2:0] NextState_sofCntl;
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//--------------------------------------------------------------------
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// Machine: sofCntl
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// Machine: sofCntl
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
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always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
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begin
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begin : sofCntl_NextState
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NextState_sofCntl <= CurrState_sofCntl;
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NextState_sofCntl <= CurrState_sofCntl;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_HCTxPortReq <= HCTxPortReq;
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortCntl <= HCTxPortCntl;
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next_SOFTimer <= SOFTimer;
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next_SOFTimer <= SOFTimer;
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next_HCTxPortCntl <= HCTxPortCntl;
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next_HCTxPortData <= HCTxPortData;
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next_HCTxPortWEn <= HCTxPortWEn;
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next_HCTxPortReq <= HCTxPortReq;
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case (CurrState_sofCntl) // synopsys parallel_case full_case
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case (CurrState_sofCntl) // synopsys parallel_case full_case
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`START_SC:
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`START_SC:
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begin
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NextState_sofCntl <= `WAIT_SOF_EN;
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NextState_sofCntl <= `WAIT_SOF_EN;
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end
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`WAIT_SOF_EN:
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`WAIT_SOF_EN:
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begin
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if (SOFEnable == 1'b1)
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if (SOFEnable == 1'b1)
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begin
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begin
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NextState_sofCntl <= `SC_WAIT_GNT;
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NextState_sofCntl <= `SC_WAIT_GNT;
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next_HCTxPortReq <= 1'b1;
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next_HCTxPortReq <= 1'b1;
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end
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end
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end
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`WAIT_SEND_RESUME:
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`WAIT_SEND_RESUME:
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begin
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if (HCTxPortRdy == 1'b1)
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if (HCTxPortRdy == 1'b1)
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begin
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begin
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NextState_sofCntl <= `CLR_WEN;
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NextState_sofCntl <= `CLR_WEN;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortWEn <= 1'b1;
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next_HCTxPortData <= 8'h00;
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next_HCTxPortData <= 8'h00;
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next_HCTxPortCntl <= `TX_RESUME_START;
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next_HCTxPortCntl <= `TX_RESUME_START;
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end
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end
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end
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`INC_TIMER:
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`INC_TIMER:
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begin
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begin
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next_HCTxPortReq <= 1'b0;
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next_HCTxPortReq <= 1'b0;
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if (SOFTimerClr == 1'b1)
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if (SOFTimerClr == 1'b1)
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next_SOFTimer <= 16'h0000;
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next_SOFTimer <= 16'h0000;
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NextState_sofCntl <= `WAIT_SOF_EN;
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NextState_sofCntl <= `WAIT_SOF_EN;
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next_SOFTimer <= 16'h0000;
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next_SOFTimer <= 16'h0000;
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end
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end
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end
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end
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`SC_WAIT_GNT:
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`SC_WAIT_GNT:
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begin
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if (HCTxPortGnt == 1'b1)
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if (HCTxPortGnt == 1'b1)
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begin
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NextState_sofCntl <= `WAIT_SEND_RESUME;
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NextState_sofCntl <= `WAIT_SEND_RESUME;
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end
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end
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`CLR_WEN:
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`CLR_WEN:
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begin
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begin
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next_HCTxPortWEn <= 1'b0;
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next_HCTxPortWEn <= 1'b0;
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NextState_sofCntl <= `INC_TIMER;
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NextState_sofCntl <= `INC_TIMER;
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : sofCntl_CurrentState
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begin
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if (rst)
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if (rst)
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CurrState_sofCntl <= `START_SC;
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CurrState_sofCntl <= `START_SC;
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else
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else
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CurrState_sofCntl <= NextState_sofCntl;
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CurrState_sofCntl <= NextState_sofCntl;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin : sofCntl_RegOutput
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begin
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if (rst)
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if (rst)
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begin
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begin
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SOFTimer <= 16'h0000;
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SOFTimer <= 16'h0000;
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HCTxPortCntl <= 8'h00;
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HCTxPortCntl <= 8'h00;
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HCTxPortData <= 8'h00;
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HCTxPortData <= 8'h00;
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