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// File : ../RTL/hostController/softransmit.v
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// Generated : 10/06/06 19:35:27
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// From : ../RTL/hostController/softransmit.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// softransmit
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//// softransmit
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbHostControl_h.v"
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`include "usbHostControl_h.v"
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module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
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module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
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input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
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input SOFSyncEn;
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input [15:0] SOFTimer;
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input clk;
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input clk;
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input rst;
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input rst;
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input sendPacketArbiterGnt;
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input sendPacketArbiterGnt;
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input sendPacketRdy;
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input sendPacketRdy;
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input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
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input SOFSyncEn;
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input [15:0]SOFTimer;
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output sendPacketArbiterReq;
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output sendPacketWEn;
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output SOFSent; // single cycle pulse
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output SOFSent; // single cycle pulse
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output SOFTimerClr; // Single cycle pulse
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output SOFTimerClr; // Single cycle pulse
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output sendPacketArbiterReq;
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output sendPacketWEn;
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wire SOFEnable;
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reg SOFSent, next_SOFSent;
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wire SOFSyncEn;
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reg SOFTimerClr, next_SOFTimerClr;
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wire [15:0] SOFTimer;
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wire clk;
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wire clk;
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wire rst;
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wire rst;
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wire sendPacketArbiterGnt;
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wire sendPacketArbiterGnt;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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reg sendPacketArbiterReq, next_sendPacketArbiterReq;
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wire sendPacketRdy;
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wire sendPacketRdy;
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reg sendPacketWEn, next_sendPacketWEn;
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reg sendPacketWEn, next_sendPacketWEn;
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wire SOFEnable;
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reg SOFSent, next_SOFSent;
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wire SOFSyncEn;
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wire [15:0]SOFTimer;
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reg SOFTimerClr, next_SOFTimerClr;
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// diagram signals declarations
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// diagram signals declarations
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reg [7:0]i, next_i;
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reg [7:0]i, next_i;
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// BINARY ENCODED state machine: SOFTx
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// BINARY ENCODED state machine: SOFTx
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`define WAIT_SOF_NOW 3'b011
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`define WAIT_SOF_NOW 3'b011
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`define SOF_FIN 3'b100
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`define SOF_FIN 3'b100
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`define DLY_SOF_CHK1 3'b101
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`define DLY_SOF_CHK1 3'b101
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`define DLY_SOF_CHK2 3'b110
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`define DLY_SOF_CHK2 3'b110
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reg [2:0]CurrState_SOFTx, NextState_SOFTx;
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reg [2:0] CurrState_SOFTx;
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reg [2:0] NextState_SOFTx;
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//--------------------------------------------------------------------
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// Machine: SOFTx
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// Machine: SOFTx
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
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begin : SOFTx_NextState
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NextState_SOFTx <= CurrState_SOFTx;
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NextState_SOFTx <= CurrState_SOFTx;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_SOFSent <= SOFSent;
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next_SOFTimerClr <= SOFTimerClr;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketArbiterReq <= sendPacketArbiterReq;
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next_sendPacketWEn <= sendPacketWEn;
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next_sendPacketWEn <= sendPacketWEn;
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next_SOFTimerClr <= SOFTimerClr;
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next_SOFSent <= SOFSent;
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next_i <= i;
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next_i <= i;
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case (CurrState_SOFTx) // synopsys parallel_case full_case
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case (CurrState_SOFTx)
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`START_STX:
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`START_STX:
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begin
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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end
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`WAIT_SOF_NEAR:
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`WAIT_SOF_NEAR:
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begin
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if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
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if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
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(SOFSyncEn == 1'b1 &&
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(SOFSyncEn == 1'b1 &&
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SOFEnable == 1'b1))
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SOFEnable == 1'b1))
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begin
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begin
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NextState_SOFTx <= `WAIT_SP_GNT;
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NextState_SOFTx <= `WAIT_SP_GNT;
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next_sendPacketArbiterReq <= 1'b1;
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next_sendPacketArbiterReq <= 1'b1;
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end
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end
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end
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`WAIT_SP_GNT:
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`WAIT_SP_GNT:
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begin
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if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
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if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
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begin
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NextState_SOFTx <= `WAIT_SOF_NOW;
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NextState_SOFTx <= `WAIT_SOF_NOW;
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end
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end
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`WAIT_SOF_NOW:
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`WAIT_SOF_NOW:
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begin
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if (SOFTimer >= `SOF_TX_TIME)
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if (SOFTimer >= `SOF_TX_TIME)
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begin
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begin
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NextState_SOFTx <= `SOF_FIN;
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NextState_SOFTx <= `SOF_FIN;
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next_sendPacketWEn <= 1'b1;
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next_sendPacketWEn <= 1'b1;
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next_SOFTimerClr <= 1'b1;
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next_SOFTimerClr <= 1'b1;
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else if (SOFEnable == 1'b0)
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else if (SOFEnable == 1'b0)
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begin
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begin
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NextState_SOFTx <= `SOF_FIN;
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NextState_SOFTx <= `SOF_FIN;
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next_SOFTimerClr <= 1'b1;
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next_SOFTimerClr <= 1'b1;
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end
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end
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end
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`SOF_FIN:
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`SOF_FIN:
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begin
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begin
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next_sendPacketWEn <= 1'b0;
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next_sendPacketWEn <= 1'b0;
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next_SOFTimerClr <= 1'b0;
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next_SOFTimerClr <= 1'b0;
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next_SOFSent <= 1'b0;
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next_SOFSent <= 1'b0;
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end
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end
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`DLY_SOF_CHK2:
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`DLY_SOF_CHK2:
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begin
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begin
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next_i <= i + 1'b1;
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next_i <= i + 1'b1;
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if (i==8'hff)
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if (i==8'hff)
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begin
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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NextState_SOFTx <= `WAIT_SOF_NEAR;
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end
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : SOFTx_CurrentState
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if (rst)
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if (rst)
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CurrState_SOFTx <= `START_STX;
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CurrState_SOFTx <= `START_STX;
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else
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else
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CurrState_SOFTx <= NextState_SOFTx;
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CurrState_SOFTx <= NextState_SOFTx;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : SOFTx_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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i <= 8'h00;
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SOFSent <= 1'b0;
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SOFSent <= 1'b0;
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SOFTimerClr <= 1'b0;
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SOFTimerClr <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketArbiterReq <= 1'b0;
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sendPacketWEn <= 1'b0;
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sendPacketWEn <= 1'b0;
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i <= 8'h00;
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end
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end
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else
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else
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begin
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begin
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i <= next_i;
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SOFSent <= next_SOFSent;
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SOFSent <= next_SOFSent;
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SOFTimerClr <= next_SOFTimerClr;
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SOFTimerClr <= next_SOFTimerClr;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketArbiterReq <= next_sendPacketArbiterReq;
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sendPacketWEn <= next_sendPacketWEn;
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sendPacketWEn <= next_sendPacketWEn;
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i <= next_i;
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end
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end
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end
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end
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endmodule
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endmodule
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