| Line 49... |
Line 49... |
//
|
//
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "usbHostControl_h.v"
|
`include "usbHostControl_h.v"
|
|
|
|
|
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
|
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, fullSpeedRate);
|
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
|
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
|
input SOFSyncEn;
|
input SOFSyncEn;
|
input [15:0] SOFTimer;
|
input [15:0] SOFTimer;
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
| Line 61... |
Line 61... |
input sendPacketRdy;
|
input sendPacketRdy;
|
output SOFSent; // single cycle pulse
|
output SOFSent; // single cycle pulse
|
output SOFTimerClr; // Single cycle pulse
|
output SOFTimerClr; // Single cycle pulse
|
output sendPacketArbiterReq;
|
output sendPacketArbiterReq;
|
output sendPacketWEn;
|
output sendPacketWEn;
|
|
input fullSpeedRate;
|
|
|
wire SOFEnable;
|
wire SOFEnable;
|
reg SOFSent, next_SOFSent;
|
reg SOFSent, next_SOFSent;
|
wire SOFSyncEn;
|
wire SOFSyncEn;
|
reg SOFTimerClr, next_SOFTimerClr;
|
reg SOFTimerClr, next_SOFTimerClr;
|
| Line 73... |
Line 74... |
wire rst;
|
wire rst;
|
wire sendPacketArbiterGnt;
|
wire sendPacketArbiterGnt;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
|
wire sendPacketRdy;
|
wire sendPacketRdy;
|
reg sendPacketWEn, next_sendPacketWEn;
|
reg sendPacketWEn, next_sendPacketWEn;
|
|
reg [15:0] SOFNearTime;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [7:0]i, next_i;
|
reg [7:0]i, next_i;
|
|
|
// BINARY ENCODED state machine: SOFTx
|
// BINARY ENCODED state machine: SOFTx
|
| Line 110... |
Line 112... |
next_i <= i;
|
next_i <= i;
|
case (CurrState_SOFTx)
|
case (CurrState_SOFTx)
|
`START_STX:
|
`START_STX:
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
NextState_SOFTx <= `WAIT_SOF_NEAR;
|
`WAIT_SOF_NEAR:
|
`WAIT_SOF_NEAR:
|
if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
|
if (SOFTimer >= SOFNearTime ||
|
(SOFSyncEn == 1'b1 &&
|
(SOFSyncEn == 1'b1 &&
|
SOFEnable == 1'b1))
|
SOFEnable == 1'b1))
|
begin
|
begin
|
NextState_SOFTx <= `WAIT_SP_GNT;
|
NextState_SOFTx <= `WAIT_SP_GNT;
|
next_sendPacketArbiterReq <= 1'b1;
|
next_sendPacketArbiterReq <= 1'b1;
|
| Line 186... |
Line 188... |
i <= 8'h00;
|
i <= 8'h00;
|
SOFSent <= 1'b0;
|
SOFSent <= 1'b0;
|
SOFTimerClr <= 1'b0;
|
SOFTimerClr <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketArbiterReq <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
sendPacketWEn <= 1'b0;
|
|
SOFNearTime <= 16'h0000;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
i <= next_i;
|
i <= next_i;
|
SOFSent <= next_SOFSent;
|
SOFSent <= next_SOFSent;
|
SOFTimerClr <= next_SOFTimerClr;
|
SOFTimerClr <= next_SOFTimerClr;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketArbiterReq <= next_sendPacketArbiterReq;
|
sendPacketWEn <= next_sendPacketWEn;
|
sendPacketWEn <= next_sendPacketWEn;
|
|
if (fullSpeedRate == 1'b1)
|
|
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN;
|
|
else
|
|
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN_LOW_SPEED;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
