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[/] [usbhostslave/] [trunk/] [RTL/] [hostSlaveMux/] [hostSlaveMux.v] - Diff between revs 5 and 9

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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// $Id: hostSlaveMux.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
`timescale 1ns / 1ps
//
 
// CVS Revision History
 
//
 
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
 
// Created
 
//
 
//
 
 
 
module hostSlaveMux (
module hostSlaveMux (
  SIEPortCtrlInToSIE,
  SIEPortCtrlInToSIE,
  SIEPortCtrlInFromHost,
  SIEPortCtrlInFromHost,
  SIEPortCtrlInFromSlave,
  SIEPortCtrlInFromSlave,
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  fullSpeedBitRateToSIE,
  fullSpeedBitRateToSIE,
  fullSpeedBitRateFromHost,
  fullSpeedBitRateFromHost,
  fullSpeedBitRateFromSlave,
  fullSpeedBitRateFromSlave,
  dataIn,
  dataIn,
  dataOut,
  dataOut,
 
  address,
  writeEn,
  writeEn,
  strobe_i,
  strobe_i,
  clk,
  clk,
  rst,
  rst,
  hostSlaveMuxSel  );
  hostSlaveMuxSel  );
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output fullSpeedBitRateToSIE;
output fullSpeedBitRateToSIE;
input fullSpeedBitRateFromHost;
input fullSpeedBitRateFromHost;
input fullSpeedBitRateFromSlave;
input fullSpeedBitRateFromSlave;
//hostSlaveMuxBI
//hostSlaveMuxBI
input [7:0] dataIn;
input [7:0] dataIn;
 
input address;
input writeEn;
input writeEn;
input strobe_i;
input strobe_i;
input clk;
input clk;
input rst;
input rst;
output [7:0] dataOut;
output [7:0] dataOut;
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reg fullSpeedBitRateToSIE;
reg fullSpeedBitRateToSIE;
wire fullSpeedBitRateFromHost;
wire fullSpeedBitRateFromHost;
wire fullSpeedBitRateFromSlave;
wire fullSpeedBitRateFromSlave;
//hostSlaveMuxBI
//hostSlaveMuxBI
wire [7:0] dataIn;
wire [7:0] dataIn;
 
wire address;
wire writeEn;
wire writeEn;
wire strobe_i;
wire strobe_i;
wire clk;
wire clk;
wire rst;
wire rst;
wire [7:0] dataOut;
wire [7:0] dataOut;
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end
end
 
 
hostSlaveMuxBI u_hostSlaveMuxBI (
hostSlaveMuxBI u_hostSlaveMuxBI (
  .dataIn(dataIn),
  .dataIn(dataIn),
  .dataOut(dataOut),
  .dataOut(dataOut),
 
  .address(address),
  .writeEn(writeEn),
  .writeEn(writeEn),
  .strobe_i(strobe_i),
  .strobe_i(strobe_i),
  .clk(clk),
  .clk(clk),
  .rst(rst),
  .rst(rst),
  .hostMode(hostMode),
  .hostMode(hostMode),

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