| Line 43... |
Line 43... |
//
|
//
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
`include "usbHostSlave_h.v"
|
`include "usbHostSlave_h.v"
|
|
|
module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
|
module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
|
hostMode, hostSlaveMuxSel);
|
hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
|
|
|
input [7:0] dataIn;
|
input [7:0] dataIn;
|
input address;
|
input address;
|
input writeEn;
|
input writeEn;
|
input strobe_i;
|
input strobe_i;
|
input clk;
|
input busClk;
|
input rst;
|
input usbClk;
|
output [7:0] dataOut;
|
output [7:0] dataOut;
|
input hostSlaveMuxSel;
|
input hostSlaveMuxSel;
|
output hostMode;
|
output hostMode;
|
|
input rstFromWire;
|
|
output rstSyncToBusClkOut;
|
|
output rstSyncToUsbClkOut;
|
|
|
wire [7:0] dataIn;
|
wire [7:0] dataIn;
|
wire address;
|
wire address;
|
wire writeEn;
|
wire writeEn;
|
wire strobe_i;
|
wire strobe_i;
|
wire clk;
|
wire busClk;
|
wire rst;
|
wire usbClk;
|
reg [7:0] dataOut;
|
reg [7:0] dataOut;
|
wire hostSlaveMuxSel;
|
wire hostSlaveMuxSel;
|
reg hostMode;
|
reg hostMode;
|
|
wire rstFromWire;
|
|
reg rstSyncToBusClkOut;
|
|
reg rstSyncToUsbClkOut;
|
|
|
//internal wire and regs
|
//internal wire and regs
|
|
reg [5:0] rstShift;
|
|
reg rstFromBus;
|
|
reg rstSyncToUsbClkFirst;
|
|
|
//sync write demux
|
//sync write demux
|
always @(posedge clk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rst == 1'b1)
|
if (rstSyncToBusClkOut == 1'b1)
|
hostMode <= 1'b0;
|
hostMode <= 1'b0;
|
else begin
|
else begin
|
if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
|
if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
|
hostMode <= dataIn[0];
|
hostMode <= dataIn[0];
|
end
|
end
|
|
if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
|
|
rstFromBus <= 1'b1;
|
|
else
|
|
rstFromBus <= 1'b0;
|
end
|
end
|
|
|
|
|
// async read mux
|
// async read mux
|
always @(address or hostMode)
|
always @(address or hostMode)
|
begin
|
begin
|
case (address)
|
case (address)
|
`HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
|
`HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
|
`HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
|
`HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
// reset control
|
|
//generate 'rstSyncToBusClk'
|
|
//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
|
|
always @(posedge busClk) begin
|
|
if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
|
|
rstShift <= 6'b111111;
|
|
else
|
|
rstShift <= {1'b0, rstShift[5:1]};
|
|
end
|
|
|
|
always @(rstShift)
|
|
rstSyncToBusClkOut <= rstShift[0];
|
|
|
|
// double sync across clock domains to generate 'forceEmptySyncToWrClk'
|
|
always @(posedge usbClk) begin
|
|
rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
|
|
rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
|
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
