OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostSlaveMux/] [hostSlaveMuxBI.v] - Diff between revs 5 and 9

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 5 Rev 9
Line 39... Line 39...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// $Id: hostSlaveMuxBI.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
`timescale 1ns / 1ps
//
 
// CVS Revision History
`include "usbHostSlave_h.v"
//
 
// $Log: not supported by cvs2svn $
 
// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
 
// Created
 
//
 
//
 
 
 
 module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
 module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
  hostMode, hostSlaveMuxSel);
  hostMode, hostSlaveMuxSel);
 
 
input [7:0] dataIn;
input [7:0] dataIn;
 
input address;
input writeEn;
input writeEn;
input strobe_i;
input strobe_i;
input clk;
input clk;
input rst;
input rst;
output [7:0] dataOut;
output [7:0] dataOut;
input hostSlaveMuxSel;
input hostSlaveMuxSel;
output hostMode;
output hostMode;
 
 
wire [7:0] dataIn;
wire [7:0] dataIn;
 
wire address;
wire writeEn;
wire writeEn;
wire strobe_i;
wire strobe_i;
wire clk;
wire clk;
wire rst;
wire rst;
reg [7:0] dataOut;
reg [7:0] dataOut;
Line 78... Line 74...
always @(posedge clk)
always @(posedge clk)
begin
begin
  if (rst == 1'b1)
  if (rst == 1'b1)
    hostMode <= 1'b0;
    hostMode <= 1'b0;
  else begin
  else begin
    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
      hostMode <= dataIn[0];
      hostMode <= dataIn[0];
  end
  end
end
end
 
 
 
 
// async read mux
// async read mux
always @(hostMode)
always @(address or hostMode)
begin
begin
  dataOut <= {7'h0, hostMode};
  case (address)
 
    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
 
    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
 
  endcase
end
end
 
 
endmodule
endmodule
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.