URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbHostControl_h.v] - Diff between revs 9 and 14

Rev 9	Rev 14
Line 27...	Line 27...

`//TXControlRegIndices`	`//TXControlRegIndices`
`define TRANS_REQ_BIT 0	`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1	`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2	`define PREAMBLE_ENABLE_BIT 2
	`define ISO_ENABLE_BIT 3

`//interruptRegIndices`	`//interruptRegIndices`
`define TRANS_DONE_BIT 0	`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1	`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2	`define CONNECTION_EVENT_BIT 2
Line 52...	Line 53...
`//TXSOFEnableIndices`	`//TXSOFEnableIndices`
`define SOF_EN_BIT 0	`define SOF_EN_BIT 0

`//SOFTimeConstants`	`//SOFTimeConstants`
//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval	//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
`define SOF_TX_TIME 16'hbb80 //Correct SOF interval for 48MHz clock	`//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer`
	`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
//`define SOF_TX_MARGIN 2	//`define SOF_TX_MARGIN 2
`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak	`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak

`//Host RXStatusRegIndices`	`//Host RXStatusRegIndices`
`define HC_CRC_ERROR_BIT 0	`define HC_CRC_ERROR_BIT 0