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// TX fifo data count register.
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// TX fifo data count register.
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// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
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// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
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// Fixed slave mode bug which caused receive fifo to be filled with
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// Fixed slave mode bug which caused receive fifo to be filled with
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// incoming data when the slave was responding with a NAK, and the
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// incoming data when the slave was responding with a NAK, and the
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// data should have been discarded.
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// data should have been discarded.
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// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
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// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
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// there was no detected activity on the USB data lines. This caused an infrequent
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// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
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// the higher level state machines are actively looking for receive packets.
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// Modified USB RX data clock recovery, so that data is sampled during the middle
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// of a USB bit period. Fixed a bug which could result in double sampling
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// of USB RX data if clock phase adjustments were required in the middle of a
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// USB packet.
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// Most significant nibble corresponds to major revision.
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// Most significant nibble corresponds to major revision.
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// Least significant nibble corresponds to minor revision.
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// Least significant nibble corresponds to minor revision.
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`define USBHOSTSLAVE_VERSION_NUM 8'h10
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`define USBHOSTSLAVE_VERSION_NUM 8'h11
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//Host slave common registers
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//Host slave common registers
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_VERSION_REG 1'b1
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`define HOST_SLAVE_VERSION_REG 1'b1
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