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https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
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// the higher level state machines are actively looking for receive packets.
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// the higher level state machines are actively looking for receive packets.
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// Modified USB RX data clock recovery, so that data is sampled during the middle
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// Modified USB RX data clock recovery, so that data is sampled during the middle
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// of a USB bit period. Fixed a bug which could result in double sampling
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// of a USB bit period. Fixed a bug which could result in double sampling
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// of USB RX data if clock phase adjustments were required in the middle of a
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// of USB RX data if clock phase adjustments were required in the middle of a
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// USB packet.
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// USB packet.
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// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
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// during migration to ActiveHDL 7.1. Released SystemC test bench.
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// Re-generated .v files using ActiveHDL 7.1
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// Replaced individual timescale directives with `include "timescale.v
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// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
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// 'usbHostSlaveAvalonWrap'
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// Most significant nibble corresponds to major revision.
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// Most significant nibble corresponds to major revision.
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// Least significant nibble corresponds to minor revision.
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// Least significant nibble corresponds to minor revision.
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`define USBHOSTSLAVE_VERSION_NUM 8'h11
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`define USBHOSTSLAVE_VERSION_NUM 8'h12
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//Host slave common registers
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//Host slave common registers
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_VERSION_REG 1'b1
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`define HOST_SLAVE_VERSION_REG 1'b1
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