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Line 46... |
// during migration to ActiveHDL 7.1. Released SystemC test bench.
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// during migration to ActiveHDL 7.1. Released SystemC test bench.
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// Re-generated .v files using ActiveHDL 7.1
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// Re-generated .v files using ActiveHDL 7.1
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// Replaced individual timescale directives with `include "timescale.v
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// Replaced individual timescale directives with `include "timescale.v
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// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
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// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
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// 'usbHostSlaveAvalonWrap'
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// 'usbHostSlaveAvalonWrap'
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// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
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// synchronizer to incoming USB wire data to avoid
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// metastability, and delay hazards. Not entirely sure, but it appears that
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// this bug caused more problems with some of the newer low power FPGAs
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// Maybe because they are more prone to problems with metastable
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// inputs that feed logic functions causing excessive high speed
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// toggle activity, and disrupting nearby cicuits.
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// Most significant nibble corresponds to major revision.
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// Most significant nibble corresponds to major revision.
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// Least significant nibble corresponds to minor revision.
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// Least significant nibble corresponds to minor revision.
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`define USBHOSTSLAVE_VERSION_NUM 8'h12
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`define USBHOSTSLAVE_VERSION_NUM 8'h13
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//Host slave common registers
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//Host slave common registers
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_CONTROL_REG 1'b0
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`define HOST_SLAVE_VERSION_REG 1'b1
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`define HOST_SLAVE_VERSION_REG 1'b1
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