| Line 64... |
Line 64... |
// the user would need to instantiate a GPIO module to control USB speed,
|
// the user would need to instantiate a GPIO module to control USB speed,
|
// D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
|
// D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
|
// Modified cross-clock synchronisation of fifo resets
|
// Modified cross-clock synchronisation of fifo resets
|
// Added usbDevice, a standalone usb device implementation of usbhostslave
|
// Added usbDevice, a standalone usb device implementation of usbhostslave
|
// no additional hardware or software required
|
// no additional hardware or software required
|
|
// Version 2.1 - October 8th 2010. Fixed issues related to accessing low speed device via hub.
|
|
// Changed USB PHY 'USBFullSpeed' edge rate control pin so that it is wired to
|
|
// 'fullSpeedPolarityToSIE', rather than 'fullSpeedBitRateToSIE'.
|
|
// Introduced delay into 'fullSpeedRate' in module writeUSBWireData.v. Thus matching
|
|
// data delay with control delay.
|
|
// Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed
|
|
// without SEO (EOP), and ensures line state is left at state J.
|
|
// Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled.
|
|
|
// Most significant nibble corresponds to major revision.
|
// Most significant nibble corresponds to major revision.
|
// Least significant nibble corresponds to minor revision.
|
// Least significant nibble corresponds to minor revision.
|
`define USBHOSTSLAVE_VERSION_NUM 8'h20
|
`define USBHOSTSLAVE_VERSION_NUM 8'h21
|
|
|
//Host slave common registers
|
//Host slave common registers
|
`define HOST_SLAVE_CONTROL_REG 1'b0
|
`define HOST_SLAVE_CONTROL_REG 1'b0
|
`define HOST_SLAVE_VERSION_REG 1'b1
|
`define HOST_SLAVE_VERSION_REG 1'b1
|
|
|
