| Line 42... |
Line 42... |
`define SC_FRAME_NUM_MSP 5'h15
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`define SC_FRAME_NUM_MSP 5'h15
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`define SC_FRAME_NUM_LSP 5'h16
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`define SC_FRAME_NUM_LSP 5'h16
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`define SCREG_BUFFER_LEN 5'h17
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`define SCREG_BUFFER_LEN 5'h17
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//SCRXStatusRegIndices
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//SCRXStatusRegIndices
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`define NAK_SET_MASK 8'h10
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`define NAK_SET_MASK 8'h10
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//`define CRC_ERROR_BIT 0
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`define SC_CRC_ERROR_BIT 0
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//`define BIT_STUFF_ERROR_BIT 1
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`define SC_BIT_STUFF_ERROR_BIT 1
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//`define RX_OVERFLOW_BIT 2
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`define SC_RX_OVERFLOW_BIT 2
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//`define RX_TIME_OUT_BIT 3
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`define SC_RX_TIME_OUT_BIT 3
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//`define NAK_SENT_BIT 4
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`define SC_NAK_SENT_BIT 4
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//`define STALL_SENT_BIT 5
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`define SC_STALL_SENT_BIT 5
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//`define ACK_RXED_BIT 6
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`define SC_ACK_RXED_BIT 6
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//`define DATA_SEQUENCE_BIT 7
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`define SC_DATA_SEQUENCE_BIT 7
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//SCEndPointControlRegIndices
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//SCEndPointControlRegIndices
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`define ENDPOINT_ENABLE_BIT 0
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`define ENDPOINT_ENABLE_BIT 0
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`define ENDPOINT_READY_BIT 1
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`define ENDPOINT_READY_BIT 1
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`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
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`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
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`define ENDPOINT_SEND_STALL_BIT 3
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`define ENDPOINT_SEND_STALL_BIT 3
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| Line 63... |
Line 63... |
`define SC_TX_LINE_STATE_LSBIT 1
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`define SC_TX_LINE_STATE_LSBIT 1
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`define SC_TX_LINE_STATE_MSBIT 2
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`define SC_TX_LINE_STATE_MSBIT 2
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`define SC_DIRECT_CONTROL_BIT 3
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`define SC_DIRECT_CONTROL_BIT 3
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`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
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`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
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`define SC_FULL_SPEED_LINE_RATE_BIT 5
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`define SC_FULL_SPEED_LINE_RATE_BIT 5
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`define SC_CONNECT_TO_HOST_BIT 6
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//SCinterruptRegIndices
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//SCinterruptRegIndices
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`define TRANS_DONE_BIT 0
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`define TRANS_DONE_BIT 0
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`define RESUME_INT_BIT 1
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`define RESUME_INT_BIT 1
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`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
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`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
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`define SOF_RECEIVED_BIT 3
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`define SOF_RECEIVED_BIT 3
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`define NAK_SENT_INT_BIT 4
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`define NAK_SENT_INT_BIT 4
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`define VBUS_DET_INT_BIT 5
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//TXTransactionTypes
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//TXTransactionTypes
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`define SC_SETUP_TRANS 0
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`define SC_SETUP_TRANS 0
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`define SC_IN_TRANS 1
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`define SC_IN_TRANS 1
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`define SC_OUTDATA_TRANS 2
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`define SC_OUTDATA_TRANS 2
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//timeOuts
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//timeOuts
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`define SC_RX_PACKET_TOUT 18
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`define SC_RX_PACKET_TOUT 18
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//line status reg
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`define VBUS_PRES_BIT 2
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`endif //usbSlaveControl_h_vdefined
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`endif //usbSlaveControl_h_vdefined
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