| Line 45... |
Line 45... |
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
|
|
|
|
module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
|
module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
|
input clk;
|
input clk;
|
input [15:0]CRC16Result;
|
input [15:0]CRC16Result;
|
input CRC16UpdateRdy;
|
input CRC16UpdateRdy;
|
input [4:0]CRC5Result;
|
input [4:0]CRC5Result;
|
input CRC5UpdateRdy;
|
input CRC5UpdateRdy;
|
|
input fullSpeedRateIn;
|
input [1:0]JBit;
|
input [1:0]JBit;
|
input [1:0]KBit;
|
input [1:0]KBit;
|
input processTxByteRdy;
|
input processTxByteRdy;
|
input rst;
|
input rst;
|
input [7:0]SIEPortCtrlIn;
|
input [7:0]SIEPortCtrlIn;
|
| Line 69... |
Line 70... |
output processTxByteWEn;
|
output processTxByteWEn;
|
output rstCRC;
|
output rstCRC;
|
output SIEPortTxRdy;
|
output SIEPortTxRdy;
|
output [7:0]TxByteOut;
|
output [7:0]TxByteOut;
|
output [7:0]TxByteOutCtrl;
|
output [7:0]TxByteOutCtrl;
|
|
output TxByteOutFullSpeedRate;
|
output USBWireCtrl;
|
output USBWireCtrl;
|
output [1:0]USBWireData;
|
output [1:0]USBWireData;
|
|
output USBWireFullSpeedRate;
|
output USBWireReq;
|
output USBWireReq;
|
output USBWireWEn;
|
output USBWireWEn;
|
|
|
wire clk;
|
wire clk;
|
reg CRC16En, next_CRC16En;
|
reg CRC16En, next_CRC16En;
|
| Line 83... |
Line 86... |
reg CRC5_8Bit, next_CRC5_8Bit;
|
reg CRC5_8Bit, next_CRC5_8Bit;
|
reg CRC5En, next_CRC5En;
|
reg CRC5En, next_CRC5En;
|
wire [4:0]CRC5Result;
|
wire [4:0]CRC5Result;
|
wire CRC5UpdateRdy;
|
wire CRC5UpdateRdy;
|
reg [7:0]CRCData, next_CRCData;
|
reg [7:0]CRCData, next_CRCData;
|
|
wire fullSpeedRateIn;
|
wire [1:0]JBit;
|
wire [1:0]JBit;
|
wire [1:0]KBit;
|
wire [1:0]KBit;
|
wire processTxByteRdy;
|
wire processTxByteRdy;
|
reg processTxByteWEn, next_processTxByteWEn;
|
reg processTxByteWEn, next_processTxByteWEn;
|
wire rst;
|
wire rst;
|
| Line 95... |
Line 99... |
wire [7:0]SIEPortDataIn;
|
wire [7:0]SIEPortDataIn;
|
reg SIEPortTxRdy, next_SIEPortTxRdy;
|
reg SIEPortTxRdy, next_SIEPortTxRdy;
|
wire SIEPortWEn;
|
wire SIEPortWEn;
|
reg [7:0]TxByteOut, next_TxByteOut;
|
reg [7:0]TxByteOut, next_TxByteOut;
|
reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
|
reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
|
|
reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
|
reg USBWireCtrl, next_USBWireCtrl;
|
reg USBWireCtrl, next_USBWireCtrl;
|
reg [1:0]USBWireData, next_USBWireData;
|
reg [1:0]USBWireData, next_USBWireData;
|
|
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
|
wire USBWireGnt;
|
wire USBWireGnt;
|
wire USBWireRdy;
|
wire USBWireRdy;
|
reg USBWireReq, next_USBWireReq;
|
reg USBWireReq, next_USBWireReq;
|
reg USBWireWEn, next_USBWireWEn;
|
reg USBWireWEn, next_USBWireWEn;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [4:0]i, next_i;
|
reg [2:0]i, next_i;
|
|
reg [15:0]resumeCnt, next_resumeCnt;
|
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
|
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
|
reg [7:0]SIEPortData, next_SIEPortData;
|
reg [7:0]SIEPortData, next_SIEPortData;
|
|
|
// BINARY ENCODED state machine: SIETx
|
// BINARY ENCODED state machine: SIETx
|
// State codes definitions:
|
// State codes definitions:
|
`define RES_ST_CHK_FIN 6'b000000
|
`define DIR_CTL_CHK_FIN 6'b000000
|
`define DIR_CTL_CHK_FIN 6'b000001
|
`define RES_ST_CHK_FIN 6'b000001
|
`define PKT_ST_CHK_PID 6'b000010
|
`define PKT_ST_CHK_PID 6'b000010
|
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
|
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
|
`define IDLE 6'b000100
|
`define IDLE 6'b000100
|
`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
|
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
|
`define PKT_ST_HS_PKT_SENT 6'b000110
|
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
|
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
|
`define PKT_ST_HS_PKT_SENT 6'b000111
|
`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
|
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
|
`define PKT_ST_SPCL_PKT_SENT 6'b001001
|
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
|
`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
|
`define PKT_ST_SPCL_PKT_SENT 6'b001010
|
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
|
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
|
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
|
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
|
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
|
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
|
`define RES_ST_S1 6'b001110
|
`define RES_ST_SND_J_1 6'b001110
|
`define RES_ST_S3 6'b001111
|
`define RES_ST_SND_J_2 6'b001111
|
`define RES_ST_S4 6'b010000
|
`define RES_ST_SND_SE0_1 6'b010000
|
`define RES_ST_S5 6'b010001
|
`define RES_ST_SND_SE0_2 6'b010001
|
`define RES_ST_S6 6'b010010
|
`define START_SIETX 6'b010010
|
`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
|
`define STX_CHK_ST 6'b010011
|
`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
|
`define STX_WAIT_BYTE 6'b010100
|
`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
|
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
|
`define START_SIETX 6'b010110
|
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
|
`define STX_CHK_ST 6'b010111
|
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
|
`define STX_WAIT_BYTE 6'b011000
|
`define RES_ST_W_RDY1 6'b011000
|
`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
|
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
|
`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
|
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
|
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
|
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
|
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
|
`define RES_ST_WAIT_GNT 6'b011100
|
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
|
`define DIR_CTL_WAIT_GNT 6'b011101
|
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
|
`define PKT_ST_HS_WAIT_RDY 6'b011110
|
`define RES_ST_WAIT_GNT 6'b011111
|
`define PKT_ST_SPCL_WAIT_RDY 6'b011111
|
`define DIR_CTL_WAIT_GNT 6'b100000
|
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
|
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
|
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
|
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
|
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
|
`define PKT_ST_SPCL_WAIT_RDY 6'b100011
|
`define RES_ST_WAIT_RDY 6'b100011
|
`define PKT_ST_HS_WAIT_RDY 6'b100100
|
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
|
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
|
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
|
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
|
`define DIR_CTL_WAIT_RDY 6'b100110
|
`define DIR_CTL_WAIT_RDY 6'b100111
|
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
|
`define RES_ST_WAIT_RDY 6'b101000
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
|
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
|
`define PKT_ST_WAIT_RDY_PKT 6'b101001
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
|
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
|
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
|
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
|
`define PKT_ST_WAIT_RDY_PKT 6'b101100
|
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
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`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
|
`define TX_LS_EOP_WAIT_GNT1 6'b101101
|
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
|
`define TX_LS_EOP_SND_SE0_2 6'b101110
|
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
|
`define TX_LS_EOP_SND_SE0_1 6'b101111
|
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
|
`define TX_LS_EOP_W_RDY1 6'b110000
|
|
`define TX_LS_EOP_SND_J 6'b110001
|
|
`define TX_LS_EOP_W_RDY2 6'b110010
|
|
`define TX_LS_EOP_W_RDY3 6'b110011
|
|
`define RES_ST_DELAY 6'b110100
|
|
`define RES_ST_W_RDY2 6'b110101
|
|
`define RES_ST_W_RDY3 6'b110110
|
|
`define RES_ST_W_RDY4 6'b110111
|
|
`define DIR_CTL_DELAY 6'b111000
|
|
|
reg [5:0]CurrState_SIETx, NextState_SIETx;
|
reg [5:0]CurrState_SIETx, NextState_SIETx;
|
|
|
|
|
// Machine: SIETx
|
// Machine: SIETx
|
|
|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
|
always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
|
begin
|
begin
|
NextState_SIETx <= CurrState_SIETx;
|
NextState_SIETx <= CurrState_SIETx;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_USBWireWEn <= USBWireWEn;
|
next_USBWireWEn <= USBWireWEn;
|
next_i <= i;
|
next_i <= i;
|
next_USBWireReq <= USBWireReq;
|
next_USBWireReq <= USBWireReq;
|
next_processTxByteWEn <= processTxByteWEn;
|
next_processTxByteWEn <= processTxByteWEn;
|
next_rstCRC <= rstCRC;
|
next_rstCRC <= rstCRC;
|
next_USBWireData <= USBWireData;
|
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
|
next_USBWireCtrl <= USBWireCtrl;
|
|
next_TxByteOut <= TxByteOut;
|
next_TxByteOut <= TxByteOut;
|
next_TxByteOutCtrl <= TxByteOutCtrl;
|
next_TxByteOutCtrl <= TxByteOutCtrl;
|
|
next_USBWireData <= USBWireData;
|
|
next_USBWireCtrl <= USBWireCtrl;
|
next_CRCData <= CRCData;
|
next_CRCData <= CRCData;
|
next_CRC5En <= CRC5En;
|
next_CRC5En <= CRC5En;
|
next_CRC5_8Bit <= CRC5_8Bit;
|
next_CRC5_8Bit <= CRC5_8Bit;
|
next_CRC16En <= CRC16En;
|
next_CRC16En <= CRC16En;
|
next_SIEPortTxRdy <= SIEPortTxRdy;
|
next_SIEPortTxRdy <= SIEPortTxRdy;
|
next_SIEPortData <= SIEPortData;
|
next_SIEPortData <= SIEPortData;
|
next_SIEPortCtrl <= SIEPortCtrl;
|
next_SIEPortCtrl <= SIEPortCtrl;
|
|
next_resumeCnt <= resumeCnt;
|
|
next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
|
case (CurrState_SIETx) // synopsys parallel_case full_case
|
case (CurrState_SIETx) // synopsys parallel_case full_case
|
`IDLE:
|
`IDLE:
|
begin
|
begin
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
| Line 207... |
Line 225... |
next_CRC5_8Bit <= 1'b0;
|
next_CRC5_8Bit <= 1'b0;
|
next_CRC16En <= 1'b0;
|
next_CRC16En <= 1'b0;
|
next_SIEPortTxRdy <= 1'b0;
|
next_SIEPortTxRdy <= 1'b0;
|
next_SIEPortData <= 8'h00;
|
next_SIEPortData <= 8'h00;
|
next_SIEPortCtrl <= 8'h00;
|
next_SIEPortCtrl <= 8'h00;
|
next_i <= 5'h0;
|
next_i <= 3'h0;
|
|
next_resumeCnt <= 16'h0000;
|
|
next_TxByteOutFullSpeedRate <= 1'b0;
|
|
next_USBWireFullSpeedRate <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`STX_CHK_ST:
|
`STX_CHK_ST:
|
begin
|
begin
|
if (SIEPortCtrl == `TX_PACKET_START)
|
if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
|
|
next_TxByteOutFullSpeedRate <= 1'b1;
|
|
//SOF and PRE always at full speed
|
|
end
|
|
else if (SIEPortCtrl == `TX_PACKET_START)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
|
|
end
|
|
else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
|
|
begin
|
|
NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
|
|
next_USBWireReq <= 1'b1;
|
end
|
end
|
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
|
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
|
begin
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
|
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
| Line 229... |
Line 261... |
end
|
end
|
else if (SIEPortCtrl == `TX_RESUME_START)
|
else if (SIEPortCtrl == `TX_RESUME_START)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_GNT;
|
NextState_SIETx <= `RES_ST_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
next_i <= 5'h0;
|
next_resumeCnt <= 16'h0000;
|
|
next_USBWireFullSpeedRate <= 1'b0;
|
|
//resume always uses low speed timing
|
end
|
end
|
end
|
end
|
`STX_WAIT_BYTE:
|
`STX_WAIT_BYTE:
|
begin
|
begin
|
next_SIEPortTxRdy <= 1'b1;
|
next_SIEPortTxRdy <= 1'b1;
|
| Line 241... |
Line 275... |
begin
|
begin
|
NextState_SIETx <= `STX_CHK_ST;
|
NextState_SIETx <= `STX_CHK_ST;
|
next_SIEPortData <= SIEPortDataIn;
|
next_SIEPortData <= SIEPortDataIn;
|
next_SIEPortCtrl <= SIEPortCtrlIn;
|
next_SIEPortCtrl <= SIEPortCtrlIn;
|
next_SIEPortTxRdy <= 1'b0;
|
next_SIEPortTxRdy <= 1'b0;
|
|
next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
|
|
next_USBWireFullSpeedRate <= fullSpeedRateIn;
|
end
|
end
|
end
|
end
|
`DIR_CTL_CHK_FIN:
|
`DIR_CTL_CHK_FIN:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_i <= i + 1'b1;
|
next_i <= i + 1'b1;
|
if (i == 5'h7)
|
if (i == 3'h7)
|
begin
|
begin
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
NextState_SIETx <= `DIR_CTL_DELAY;
|
end
|
end
|
end
|
end
|
`DIR_CTL_WAIT_GNT:
|
`DIR_CTL_WAIT_GNT:
|
begin
|
begin
|
next_i <= 5'h0;
|
next_i <= 3'h0;
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
end
|
end
|
end
|
end
|
| Line 275... |
Line 311... |
next_USBWireData <= SIEPortData[1:0];
|
next_USBWireData <= SIEPortData[1:0];
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
|
`DIR_CTL_DELAY:
|
|
begin
|
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
|
end
|
`PKT_ST_CHK_PID:
|
`PKT_ST_CHK_PID:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
if (SIEPortData[1:0] == `TOKEN)
|
if (SIEPortData[1:0] == `TOKEN)
|
begin
|
begin
|
| Line 421... |
Line 461... |
end
|
end
|
end
|
end
|
`PKT_ST_SPCL_PKT_SENT:
|
`PKT_ST_SPCL_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
|
|
end
|
|
`PKT_ST_SPCL_SEND_IDLE1:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
|
|
next_USBWireData <= JBit;
|
|
next_USBWireCtrl <= `TRI_STATE;
|
|
next_USBWireWEn <= 1'b1;
|
|
end
|
|
end
|
|
`PKT_ST_SPCL_SEND_IDLE2:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
|
|
next_USBWireData <= JBit;
|
|
next_USBWireCtrl <= `TRI_STATE;
|
|
next_USBWireWEn <= 1'b1;
|
|
end
|
|
end
|
|
`PKT_ST_SPCL_SEND_IDLE3:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_SPCL_WAIT_RDY:
|
`PKT_ST_SPCL_WAIT_RDY:
|
begin
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
| Line 460... |
Line 473... |
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
end
|
`PKT_ST_SPCL_WAIT_WIRE:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
|
|
next_USBWireData <= JBit;
|
|
next_USBWireCtrl <= `TRI_STATE;
|
|
next_USBWireWEn <= 1'b1;
|
|
end
|
|
end
|
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
end
|
end
|
| Line 572... |
Line 575... |
end
|
end
|
end
|
end
|
`RES_ST_CHK_FIN:
|
`RES_ST_CHK_FIN:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (i == `RESUME_LEN)
|
if (resumeCnt == `HOST_TX_RESUME_TIME)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S1;
|
NextState_SIETx <= `RES_ST_W_RDY1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `RES_ST_DELAY;
|
|
end
|
end
|
end
|
|
`RES_ST_SND_J_1:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `RES_ST_W_RDY4;
|
|
end
|
|
`RES_ST_SND_J_2:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
next_USBWireReq <= 1'b0;
|
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
|
next_USBWireFullSpeedRate <= fullSpeedRateIn;
|
end
|
end
|
`RES_ST_S1:
|
`RES_ST_SND_SE0_1:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `RES_ST_W_RDY2;
|
|
end
|
|
`RES_ST_SND_SE0_2:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `RES_ST_W_RDY3;
|
|
end
|
|
`RES_ST_W_RDY1:
|
begin
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S3;
|
NextState_SIETx <= `RES_ST_SND_SE0_1;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
`RES_ST_S3:
|
`RES_ST_WAIT_GNT:
|
|
begin
|
|
if (USBWireGnt == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
|
end
|
|
end
|
|
`RES_ST_WAIT_RDY:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
|
next_USBWireData <= KBit;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
next_USBWireWEn <= 1'b1;
|
|
next_resumeCnt <= resumeCnt + 1'b1;
|
|
end
|
|
end
|
|
`RES_ST_DELAY:
|
|
begin
|
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
|
end
|
|
`RES_ST_W_RDY2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S4;
|
NextState_SIETx <= `RES_ST_SND_SE0_2;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
`RES_ST_S4:
|
`RES_ST_W_RDY3:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S5;
|
NextState_SIETx <= `RES_ST_SND_J_1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
`RES_ST_S5:
|
`RES_ST_W_RDY4:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S6;
|
NextState_SIETx <= `RES_ST_SND_J_2;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
`RES_ST_S6:
|
`TX_LS_EOP_WAIT_GNT1:
|
|
begin
|
|
if (USBWireGnt == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
|
|
end
|
|
end
|
|
`TX_LS_EOP_SND_SE0_2:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
|
|
end
|
|
`TX_LS_EOP_SND_SE0_1:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
|
|
end
|
|
`TX_LS_EOP_W_RDY1:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
next_USBWireWEn <= 1'b1;
|
|
end
|
|
end
|
|
`TX_LS_EOP_SND_J:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`RES_ST_WAIT_GNT:
|
`TX_LS_EOP_W_RDY2:
|
begin
|
begin
|
if (USBWireGnt == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
end
|
`RES_ST_WAIT_RDY:
|
`TX_LS_EOP_W_RDY3:
|
begin
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
NextState_SIETx <= `TX_LS_EOP_SND_J;
|
next_USBWireData <= KBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_i <= i + 1'b1;
|
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 669... |
Line 742... |
begin
|
begin
|
USBWireWEn <= 1'b0;
|
USBWireWEn <= 1'b0;
|
USBWireReq <= 1'b0;
|
USBWireReq <= 1'b0;
|
processTxByteWEn <= 1'b0;
|
processTxByteWEn <= 1'b0;
|
rstCRC <= 1'b0;
|
rstCRC <= 1'b0;
|
USBWireData <= 2'b00;
|
USBWireFullSpeedRate <= 1'b0;
|
USBWireCtrl <= `TRI_STATE;
|
|
TxByteOut <= 8'h00;
|
TxByteOut <= 8'h00;
|
TxByteOutCtrl <= 8'h00;
|
TxByteOutCtrl <= 8'h00;
|
|
USBWireData <= 2'b00;
|
|
USBWireCtrl <= `TRI_STATE;
|
CRCData <= 8'h00;
|
CRCData <= 8'h00;
|
CRC5En <= 1'b0;
|
CRC5En <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC16En <= 1'b0;
|
CRC16En <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
i <= 5'h0;
|
TxByteOutFullSpeedRate <= 1'b0;
|
|
i <= 3'h0;
|
SIEPortData <= 8'h00;
|
SIEPortData <= 8'h00;
|
SIEPortCtrl <= 8'h00;
|
SIEPortCtrl <= 8'h00;
|
|
resumeCnt <= 16'h0000;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
USBWireWEn <= next_USBWireWEn;
|
USBWireWEn <= next_USBWireWEn;
|
USBWireReq <= next_USBWireReq;
|
USBWireReq <= next_USBWireReq;
|
processTxByteWEn <= next_processTxByteWEn;
|
processTxByteWEn <= next_processTxByteWEn;
|
rstCRC <= next_rstCRC;
|
rstCRC <= next_rstCRC;
|
USBWireData <= next_USBWireData;
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
USBWireCtrl <= next_USBWireCtrl;
|
|
TxByteOut <= next_TxByteOut;
|
TxByteOut <= next_TxByteOut;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
|
USBWireData <= next_USBWireData;
|
|
USBWireCtrl <= next_USBWireCtrl;
|
CRCData <= next_CRCData;
|
CRCData <= next_CRCData;
|
CRC5En <= next_CRC5En;
|
CRC5En <= next_CRC5En;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC16En <= next_CRC16En;
|
CRC16En <= next_CRC16En;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
|
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
|
i <= next_i;
|
i <= next_i;
|
SIEPortData <= next_SIEPortData;
|
SIEPortData <= next_SIEPortData;
|
SIEPortCtrl <= next_SIEPortCtrl;
|
SIEPortCtrl <= next_SIEPortCtrl;
|
|
resumeCnt <= next_resumeCnt;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
