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// File : ../RTL/serialInterfaceEngine/SIETransmitter.v
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// Generated : 10/06/06 19:35:31
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// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// SIETransmitter
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//// SIETransmitter
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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| Line 40... |
Line 45... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
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input clk;
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input [15:0]CRC16Result;
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input [15:0]CRC16Result;
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input CRC16UpdateRdy;
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input CRC16UpdateRdy;
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input [4:0]CRC5Result;
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input [4:0]CRC5Result;
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input CRC5UpdateRdy;
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input CRC5UpdateRdy;
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input fullSpeedRateIn;
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input [1:0]JBit;
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input [1:0]JBit;
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input [1:0]KBit;
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input [1:0]KBit;
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input processTxByteRdy;
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input rst;
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input [7:0]SIEPortCtrlIn;
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input [7:0]SIEPortCtrlIn;
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input [7:0]SIEPortDataIn;
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input [7:0]SIEPortDataIn;
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input SIEPortWEn;
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input SIEPortWEn;
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input USBWireGnt;
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input USBWireGnt;
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input USBWireRdy;
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input USBWireRdy;
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input clk;
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input fullSpeedRateIn;
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input processTxByteRdy;
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input rst;
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output CRC16En;
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output CRC16En;
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output CRC5_8Bit;
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output CRC5En;
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output CRC5En;
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output CRC5_8Bit;
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output [7:0]CRCData;
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output [7:0]CRCData;
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output processTxByteWEn;
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output rstCRC;
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output SIEPortTxRdy;
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output SIEPortTxRdy;
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output [7:0]TxByteOut;
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output [7:0]TxByteOutCtrl;
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output [7:0]TxByteOutCtrl;
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output TxByteOutFullSpeedRate;
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output TxByteOutFullSpeedRate;
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output [7:0] TxByteOut;
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output USBWireCtrl;
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output USBWireCtrl;
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output [1:0]USBWireData;
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output [1:0]USBWireData;
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output USBWireFullSpeedRate;
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output USBWireFullSpeedRate;
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output USBWireReq;
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output USBWireReq;
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output USBWireWEn;
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output USBWireWEn;
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output processTxByteWEn;
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output rstCRC;
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wire clk;
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reg CRC16En, next_CRC16En;
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reg CRC16En, next_CRC16En;
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wire [15:0]CRC16Result;
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wire [15:0]CRC16Result;
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wire CRC16UpdateRdy;
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wire CRC16UpdateRdy;
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reg CRC5_8Bit, next_CRC5_8Bit;
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reg CRC5En, next_CRC5En;
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reg CRC5En, next_CRC5En;
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wire [4:0]CRC5Result;
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wire [4:0]CRC5Result;
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wire CRC5UpdateRdy;
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wire CRC5UpdateRdy;
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reg CRC5_8Bit, next_CRC5_8Bit;
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reg [7:0]CRCData, next_CRCData;
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reg [7:0]CRCData, next_CRCData;
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wire fullSpeedRateIn;
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wire [1:0]JBit;
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wire [1:0]JBit;
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wire [1:0]KBit;
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wire [1:0]KBit;
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wire processTxByteRdy;
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reg processTxByteWEn, next_processTxByteWEn;
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wire rst;
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reg rstCRC, next_rstCRC;
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wire [7:0]SIEPortCtrlIn;
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wire [7:0]SIEPortCtrlIn;
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wire [7:0]SIEPortDataIn;
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wire [7:0]SIEPortDataIn;
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reg SIEPortTxRdy, next_SIEPortTxRdy;
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reg SIEPortTxRdy, next_SIEPortTxRdy;
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wire SIEPortWEn;
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wire SIEPortWEn;
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reg [7:0]TxByteOut, next_TxByteOut;
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reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
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reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
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reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
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reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
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reg [7:0] TxByteOut, next_TxByteOut;
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reg USBWireCtrl, next_USBWireCtrl;
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reg USBWireCtrl, next_USBWireCtrl;
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reg [1:0]USBWireData, next_USBWireData;
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reg [1:0]USBWireData, next_USBWireData;
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reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
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reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
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wire USBWireGnt;
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wire USBWireGnt;
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wire USBWireRdy;
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wire USBWireRdy;
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reg USBWireReq, next_USBWireReq;
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reg USBWireReq, next_USBWireReq;
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reg USBWireWEn, next_USBWireWEn;
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reg USBWireWEn, next_USBWireWEn;
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wire clk;
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wire fullSpeedRateIn;
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wire processTxByteRdy;
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reg processTxByteWEn, next_processTxByteWEn;
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wire rst;
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reg rstCRC, next_rstCRC;
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// diagram signals declarations
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// diagram signals declarations
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reg [2:0]i, next_i;
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reg [15:0]resumeCnt, next_resumeCnt;
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reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortData, next_SIEPortData;
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reg [7:0]SIEPortData, next_SIEPortData;
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reg [2:0]i, next_i;
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reg [15:0]resumeCnt, next_resumeCnt;
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// BINARY ENCODED state machine: SIETx
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// BINARY ENCODED state machine: SIETx
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// State codes definitions:
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// State codes definitions:
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`define DIR_CTL_CHK_FIN 6'b000000
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`define DIR_CTL_CHK_FIN 6'b000000
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`define RES_ST_CHK_FIN 6'b000001
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`define RES_ST_CHK_FIN 6'b000001
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| Line 140... |
Line 145... |
`define STX_CHK_ST 6'b010011
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`define STX_CHK_ST 6'b010011
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`define STX_WAIT_BYTE 6'b010100
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`define STX_WAIT_BYTE 6'b010100
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
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`define RES_ST_W_RDY1 6'b011000
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
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`define DIR_CTL_WAIT_GNT 6'b011011
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`define RES_ST_WAIT_GNT 6'b011100
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`define RES_ST_WAIT_GNT 6'b011100
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`define DIR_CTL_WAIT_GNT 6'b011101
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`define PKT_ST_HS_WAIT_RDY 6'b011101
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`define PKT_ST_HS_WAIT_RDY 6'b011110
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`define DIR_CTL_WAIT_RDY 6'b011110
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`define PKT_ST_SPCL_WAIT_RDY 6'b011111
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`define PKT_ST_SPCL_WAIT_RDY 6'b011111
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
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`define RES_ST_WAIT_RDY 6'b100011
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`define RES_ST_WAIT_RDY 6'b100011
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
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`define DIR_CTL_WAIT_RDY 6'b100110
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
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`define PKT_ST_WAIT_RDY_PKT 6'b101000
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`define PKT_ST_WAIT_RDY_PKT 6'b101001
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`define RES_ST_W_RDY1 6'b101001
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`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
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`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
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`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
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`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
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`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
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`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
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`define TX_LS_EOP_WAIT_GNT1 6'b101101
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`define TX_LS_EOP_WAIT_GNT1 6'b101101
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`define TX_LS_EOP_SND_SE0_2 6'b101110
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`define TX_LS_EOP_SND_SE0_2 6'b101110
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Line 179... |
`define RES_ST_W_RDY2 6'b110101
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`define RES_ST_W_RDY2 6'b110101
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`define RES_ST_W_RDY3 6'b110110
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`define RES_ST_W_RDY3 6'b110110
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`define RES_ST_W_RDY4 6'b110111
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`define RES_ST_W_RDY4 6'b110111
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`define DIR_CTL_DELAY 6'b111000
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`define DIR_CTL_DELAY 6'b111000
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reg [5:0]CurrState_SIETx, NextState_SIETx;
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reg [5:0] CurrState_SIETx;
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reg [5:0] NextState_SIETx;
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//--------------------------------------------------------------------
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// Machine: SIETx
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// Machine: SIETx
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
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begin : SIETx_NextState
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NextState_SIETx <= CurrState_SIETx;
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NextState_SIETx <= CurrState_SIETx;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_USBWireWEn <= USBWireWEn;
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next_i <= i;
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next_USBWireReq <= USBWireReq;
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next_processTxByteWEn <= processTxByteWEn;
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next_processTxByteWEn <= processTxByteWEn;
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next_rstCRC <= rstCRC;
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next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
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next_TxByteOut <= TxByteOut;
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next_TxByteOut <= TxByteOut;
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next_TxByteOutCtrl <= TxByteOutCtrl;
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next_TxByteOutCtrl <= TxByteOutCtrl;
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next_USBWireData <= USBWireData;
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next_USBWireData <= USBWireData;
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next_USBWireCtrl <= USBWireCtrl;
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next_USBWireCtrl <= USBWireCtrl;
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next_USBWireReq <= USBWireReq;
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next_USBWireWEn <= USBWireWEn;
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next_rstCRC <= rstCRC;
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next_CRCData <= CRCData;
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next_CRCData <= CRCData;
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next_CRC5En <= CRC5En;
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next_CRC5En <= CRC5En;
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next_CRC5_8Bit <= CRC5_8Bit;
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next_CRC5_8Bit <= CRC5_8Bit;
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next_CRC16En <= CRC16En;
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next_CRC16En <= CRC16En;
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next_SIEPortTxRdy <= SIEPortTxRdy;
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next_SIEPortTxRdy <= SIEPortTxRdy;
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next_SIEPortData <= SIEPortData;
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next_SIEPortData <= SIEPortData;
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next_SIEPortCtrl <= SIEPortCtrl;
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next_SIEPortCtrl <= SIEPortCtrl;
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next_i <= i;
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next_resumeCnt <= resumeCnt;
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next_resumeCnt <= resumeCnt;
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next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
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next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
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case (CurrState_SIETx) // synopsys parallel_case full_case
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next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
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case (CurrState_SIETx)
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`IDLE:
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`IDLE:
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begin
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NextState_SIETx <= `STX_WAIT_BYTE;
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NextState_SIETx <= `STX_WAIT_BYTE;
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end
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`START_SIETX:
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`START_SIETX:
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begin
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begin
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next_processTxByteWEn <= 1'b0;
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next_processTxByteWEn <= 1'b0;
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next_TxByteOut <= 8'h00;
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next_TxByteOut <= 8'h00;
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next_TxByteOutCtrl <= 8'h00;
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next_TxByteOutCtrl <= 8'h00;
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| Line 232... |
Line 239... |
next_TxByteOutFullSpeedRate <= 1'b0;
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next_TxByteOutFullSpeedRate <= 1'b0;
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next_USBWireFullSpeedRate <= 1'b0;
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next_USBWireFullSpeedRate <= 1'b0;
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NextState_SIETx <= `STX_WAIT_BYTE;
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NextState_SIETx <= `STX_WAIT_BYTE;
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end
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end
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`STX_CHK_ST:
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`STX_CHK_ST:
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begin
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if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
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if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
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begin
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begin
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NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
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NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
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next_TxByteOutFullSpeedRate <= 1'b1;
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next_TxByteOutFullSpeedRate <= 1'b1;
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//SOF and PRE always at full speed
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//SOF and PRE always at full speed
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end
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end
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else if (SIEPortCtrl == `TX_PACKET_START)
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else if (SIEPortCtrl == `TX_PACKET_START)
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begin
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NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
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NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
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end
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else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
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else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
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begin
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begin
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NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
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NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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end
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end
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| Line 254... |
Line 258... |
begin
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begin
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NextState_SIETx <= `DIR_CTL_WAIT_GNT;
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NextState_SIETx <= `DIR_CTL_WAIT_GNT;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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end
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end
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else if (SIEPortCtrl == `TX_IDLE)
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else if (SIEPortCtrl == `TX_IDLE)
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begin
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NextState_SIETx <= `IDLE;
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NextState_SIETx <= `IDLE;
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end
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else if (SIEPortCtrl == `TX_RESUME_START)
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else if (SIEPortCtrl == `TX_RESUME_START)
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begin
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begin
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NextState_SIETx <= `RES_ST_WAIT_GNT;
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NextState_SIETx <= `RES_ST_WAIT_GNT;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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next_resumeCnt <= 16'h0000;
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next_resumeCnt <= 16'h0000;
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next_USBWireFullSpeedRate <= 1'b0;
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next_USBWireFullSpeedRate <= 1'b0;
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//resume always uses low speed timing
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//resume always uses low speed timing
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end
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end
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end
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`STX_WAIT_BYTE:
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`STX_WAIT_BYTE:
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begin
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begin
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next_SIEPortTxRdy <= 1'b1;
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next_SIEPortTxRdy <= 1'b1;
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if (SIEPortWEn == 1'b1)
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if (SIEPortWEn == 1'b1)
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begin
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begin
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| Line 289... |
Line 290... |
begin
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begin
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NextState_SIETx <= `STX_WAIT_BYTE;
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NextState_SIETx <= `STX_WAIT_BYTE;
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next_USBWireReq <= 1'b0;
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next_USBWireReq <= 1'b0;
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end
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end
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else
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else
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begin
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NextState_SIETx <= `DIR_CTL_DELAY;
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NextState_SIETx <= `DIR_CTL_DELAY;
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end
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end
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end
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`DIR_CTL_WAIT_GNT:
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`DIR_CTL_WAIT_GNT:
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begin
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begin
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next_i <= 3'h0;
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next_i <= 3'h0;
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if (USBWireGnt == 1'b1)
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if (USBWireGnt == 1'b1)
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begin
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NextState_SIETx <= `DIR_CTL_WAIT_RDY;
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NextState_SIETx <= `DIR_CTL_WAIT_RDY;
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end
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end
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end
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`DIR_CTL_WAIT_RDY:
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`DIR_CTL_WAIT_RDY:
|
begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_SIETx <= `DIR_CTL_CHK_FIN;
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NextState_SIETx <= `DIR_CTL_CHK_FIN;
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next_USBWireData <= SIEPortData[1:0];
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next_USBWireData <= SIEPortData[1:0];
|
next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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end
|
end
|
end
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|
`DIR_CTL_DELAY:
|
`DIR_CTL_DELAY:
|
begin
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|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
end
|
|
`PKT_ST_CHK_PID:
|
`PKT_ST_CHK_PID:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
if (SIEPortData[1:0] == `TOKEN)
|
if (SIEPortData[1:0] == `TOKEN)
|
begin
|
|
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
|
end
|
|
else if (SIEPortData[1:0] == `HANDSHAKE)
|
else if (SIEPortData[1:0] == `HANDSHAKE)
|
begin
|
|
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
|
end
|
|
else if (SIEPortData[1:0] == `DATA)
|
else if (SIEPortData[1:0] == `DATA)
|
begin
|
|
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
|
end
|
|
else if (SIEPortData[1:0] == `SPECIAL)
|
else if (SIEPortData[1:0] == `SPECIAL)
|
begin
|
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
|
end
|
end
|
end
|
|
`PKT_ST_WAIT_RDY_PKT:
|
`PKT_ST_WAIT_RDY_PKT:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_CHK_PID;
|
NextState_SIETx <= `PKT_ST_CHK_PID;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= `SYNC_BYTE;
|
next_TxByteOut <= `SYNC_BYTE;
|
next_TxByteOutCtrl <= `DATA_START;
|
next_TxByteOutCtrl <= `DATA_START;
|
end
|
end
|
end
|
|
`PKT_ST_DATA_CRC_PKT_SENT1:
|
`PKT_ST_DATA_CRC_PKT_SENT1:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
|
end
|
end
|
| Line 356... |
Line 339... |
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_DATA_CRC_WAIT_RDY1:
|
`PKT_ST_DATA_CRC_WAIT_RDY1:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= ~CRC16Result[7:0];
|
next_TxByteOut <= ~CRC16Result[7:0];
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
end
|
|
`PKT_ST_DATA_CRC_WAIT_RDY2:
|
`PKT_ST_DATA_CRC_WAIT_RDY2:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= ~CRC16Result[15:8];
|
next_TxByteOut <= ~CRC16Result[15:8];
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
|
`PKT_ST_DATA_DATA_CHK_STOP:
|
`PKT_ST_DATA_DATA_CHK_STOP:
|
begin
|
|
if (SIEPortCtrl == `TX_PACKET_STOP)
|
if (SIEPortCtrl == `TX_PACKET_STOP)
|
begin
|
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
|
end
|
|
else
|
else
|
begin
|
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
|
end
|
|
end
|
|
`PKT_ST_DATA_DATA_PKT_SENT:
|
`PKT_ST_DATA_DATA_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
end
|
end
|
| Line 420... |
Line 393... |
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
end
|
end
|
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
|
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
|
begin
|
|
if (CRC16UpdateRdy == 1'b1)
|
if (CRC16UpdateRdy == 1'b1)
|
begin
|
|
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
|
end
|
|
end
|
|
`PKT_ST_DATA_PID_PKT_SENT:
|
`PKT_ST_DATA_PID_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
next_rstCRC <= 1'b0;
|
next_rstCRC <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_DATA_PID_WAIT_RDY:
|
`PKT_ST_DATA_PID_WAIT_RDY:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_rstCRC <= 1'b1;
|
next_rstCRC <= 1'b1;
|
end
|
end
|
end
|
|
`PKT_ST_HS_PKT_SENT:
|
`PKT_ST_HS_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_HS_WAIT_RDY:
|
`PKT_ST_HS_WAIT_RDY:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
|
`PKT_ST_SPCL_PKT_SENT:
|
`PKT_ST_SPCL_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_SPCL_WAIT_RDY:
|
`PKT_ST_SPCL_WAIT_RDY:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
end
|
end
|
| Line 508... |
Line 471... |
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
end
|
end
|
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
|
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
|
begin
|
|
if (CRC5UpdateRdy == 1'b1)
|
if (CRC5UpdateRdy == 1'b1)
|
begin
|
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
|
end
|
|
end
|
|
`PKT_ST_TKN_CRC_PKT_SENT:
|
`PKT_ST_TKN_CRC_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
| Line 549... |
Line 508... |
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
|
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
end
|
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
|
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
|
begin
|
|
if (CRC5UpdateRdy == 1'b1)
|
if (CRC5UpdateRdy == 1'b1)
|
begin
|
|
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
|
end
|
|
end
|
|
`PKT_ST_TKN_PID_PKT_SENT:
|
`PKT_ST_TKN_PID_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
next_rstCRC <= 1'b0;
|
next_rstCRC <= 1'b0;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_TKN_PID_WAIT_RDY:
|
`PKT_ST_TKN_PID_WAIT_RDY:
|
begin
|
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_rstCRC <= 1'b1;
|
next_rstCRC <= 1'b1;
|
end
|
end
|
end
|
|
`RES_ST_CHK_FIN:
|
`RES_ST_CHK_FIN:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (resumeCnt == `HOST_TX_RESUME_TIME)
|
if (resumeCnt == `HOST_TX_RESUME_TIME)
|
begin
|
|
NextState_SIETx <= `RES_ST_W_RDY1;
|
NextState_SIETx <= `RES_ST_W_RDY1;
|
end
|
|
else
|
else
|
begin
|
|
NextState_SIETx <= `RES_ST_DELAY;
|
NextState_SIETx <= `RES_ST_DELAY;
|
end
|
end
|
end
|
|
`RES_ST_SND_J_1:
|
`RES_ST_SND_J_1:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_SIETx <= `RES_ST_W_RDY4;
|
NextState_SIETx <= `RES_ST_W_RDY4;
|
end
|
end
|
| Line 606... |
Line 555... |
`RES_ST_SND_SE0_2:
|
`RES_ST_SND_SE0_2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_SIETx <= `RES_ST_W_RDY3;
|
NextState_SIETx <= `RES_ST_W_RDY3;
|
end
|
end
|
`RES_ST_W_RDY1:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `RES_ST_SND_SE0_1;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
next_USBWireWEn <= 1'b1;
|
|
end
|
|
end
|
|
`RES_ST_WAIT_GNT:
|
`RES_ST_WAIT_GNT:
|
begin
|
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
begin
|
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
end
|
|
end
|
|
`RES_ST_WAIT_RDY:
|
`RES_ST_WAIT_RDY:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
next_USBWireData <= KBit;
|
next_USBWireData <= KBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_resumeCnt <= resumeCnt + 1'b1;
|
next_resumeCnt <= resumeCnt + 1'b1;
|
end
|
end
|
|
`RES_ST_W_RDY1:
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_SIETx <= `RES_ST_SND_SE0_1;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
`RES_ST_DELAY:
|
`RES_ST_DELAY:
|
begin
|
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
end
|
|
`RES_ST_W_RDY2:
|
`RES_ST_W_RDY2:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_SND_SE0_2;
|
NextState_SIETx <= `RES_ST_SND_SE0_2;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
`RES_ST_W_RDY3:
|
`RES_ST_W_RDY3:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_SND_J_1;
|
NextState_SIETx <= `RES_ST_SND_J_1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
`RES_ST_W_RDY4:
|
`RES_ST_W_RDY4:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_SND_J_2;
|
NextState_SIETx <= `RES_ST_SND_J_2;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
`TX_LS_EOP_WAIT_GNT1:
|
`TX_LS_EOP_WAIT_GNT1:
|
begin
|
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
begin
|
|
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
|
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
|
end
|
|
end
|
|
`TX_LS_EOP_SND_SE0_2:
|
`TX_LS_EOP_SND_SE0_2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
|
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
|
end
|
end
|
| Line 686... |
Line 615... |
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
|
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
|
end
|
end
|
`TX_LS_EOP_W_RDY1:
|
`TX_LS_EOP_W_RDY1:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
`TX_LS_EOP_SND_J:
|
`TX_LS_EOP_SND_J:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`TX_LS_EOP_W_RDY2:
|
`TX_LS_EOP_W_RDY2:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
|
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
`TX_LS_EOP_W_RDY3:
|
`TX_LS_EOP_W_RDY3:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `TX_LS_EOP_SND_J;
|
NextState_SIETx <= `TX_LS_EOP_SND_J;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : SIETx_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_SIETx <= `START_SIETX;
|
CurrState_SIETx <= `START_SIETX;
|
else
|
else
|
CurrState_SIETx <= NextState_SIETx;
|
CurrState_SIETx <= NextState_SIETx;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : SIETx_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
USBWireWEn <= 1'b0;
|
SIEPortData <= 8'h00;
|
USBWireReq <= 1'b0;
|
SIEPortCtrl <= 8'h00;
|
|
i <= 3'h0;
|
|
resumeCnt <= 16'h0000;
|
processTxByteWEn <= 1'b0;
|
processTxByteWEn <= 1'b0;
|
rstCRC <= 1'b0;
|
|
USBWireFullSpeedRate <= 1'b0;
|
|
TxByteOut <= 8'h00;
|
TxByteOut <= 8'h00;
|
TxByteOutCtrl <= 8'h00;
|
TxByteOutCtrl <= 8'h00;
|
USBWireData <= 2'b00;
|
USBWireData <= 2'b00;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireCtrl <= `TRI_STATE;
|
|
USBWireReq <= 1'b0;
|
|
USBWireWEn <= 1'b0;
|
|
rstCRC <= 1'b0;
|
CRCData <= 8'h00;
|
CRCData <= 8'h00;
|
CRC5En <= 1'b0;
|
CRC5En <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC16En <= 1'b0;
|
CRC16En <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
TxByteOutFullSpeedRate <= 1'b0;
|
TxByteOutFullSpeedRate <= 1'b0;
|
i <= 3'h0;
|
USBWireFullSpeedRate <= 1'b0;
|
SIEPortData <= 8'h00;
|
|
SIEPortCtrl <= 8'h00;
|
|
resumeCnt <= 16'h0000;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
USBWireWEn <= next_USBWireWEn;
|
SIEPortData <= next_SIEPortData;
|
USBWireReq <= next_USBWireReq;
|
SIEPortCtrl <= next_SIEPortCtrl;
|
|
i <= next_i;
|
|
resumeCnt <= next_resumeCnt;
|
processTxByteWEn <= next_processTxByteWEn;
|
processTxByteWEn <= next_processTxByteWEn;
|
rstCRC <= next_rstCRC;
|
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
|
TxByteOut <= next_TxByteOut;
|
TxByteOut <= next_TxByteOut;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
USBWireData <= next_USBWireData;
|
USBWireData <= next_USBWireData;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireCtrl <= next_USBWireCtrl;
|
|
USBWireReq <= next_USBWireReq;
|
|
USBWireWEn <= next_USBWireWEn;
|
|
rstCRC <= next_rstCRC;
|
CRCData <= next_CRCData;
|
CRCData <= next_CRCData;
|
CRC5En <= next_CRC5En;
|
CRC5En <= next_CRC5En;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC16En <= next_CRC16En;
|
CRC16En <= next_CRC16En;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
|
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
|
i <= next_i;
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
SIEPortData <= next_SIEPortData;
|
|
SIEPortCtrl <= next_SIEPortCtrl;
|
|
resumeCnt <= next_resumeCnt;
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
