| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// SIETransmitter
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\SIETransmitter.v
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// $Id: SIETransmitter.v,v 1.2 2004-12-18 14:36:14 sfielding Exp $
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// Generated : 09/27/04 21:05:15
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// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\SIETransmitter.asf
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// By : FSM2VHDL ver. 4.0.5.2
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOut, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst, rstCRC);
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module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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input clk;
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input [15:0] CRC16Result;
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input [15:0] CRC16Result;
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input CRC16UpdateRdy;
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input CRC16UpdateRdy;
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input [4:0] CRC5Result;
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input [4:0] CRC5Result;
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input CRC5UpdateRdy;
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input CRC5UpdateRdy;
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input [1:0] JBit;
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input [1:0] JBit;
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input [1:0] KBit;
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input [1:0] KBit;
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input processTxByteRdy;
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input rst;
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input [7:0] SIEPortCtrlIn;
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input [7:0] SIEPortCtrlIn;
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input [7:0] SIEPortDataIn;
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input [7:0] SIEPortDataIn;
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input SIEPortWEn;
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input SIEPortWEn;
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input USBWireGnt;
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input USBWireGnt;
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input USBWireRdy;
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input USBWireRdy;
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input clk;
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input processTxByteRdy;
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input rst;
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output CRC16En;
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output CRC16En;
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output CRC5En;
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output CRC5_8Bit;
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output CRC5_8Bit;
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output CRC5En;
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output [7:0] CRCData;
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output [7:0] CRCData;
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|
output processTxByteWEn;
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output rstCRC;
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output SIEPortTxRdy;
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output SIEPortTxRdy;
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output [7:0] TxByteOutCtrl;
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|
output [7:0] TxByteOut;
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output [7:0] TxByteOut;
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output [7:0]TxByteOutCtrl;
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output USBWireCtrl;
|
output USBWireCtrl;
|
output [1:0] USBWireData;
|
output [1:0] USBWireData;
|
output USBWireReq;
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output USBWireReq;
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output USBWireWEn;
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output USBWireWEn;
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output processTxByteWEn;
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output rstCRC;
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|
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wire clk;
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reg CRC16En, next_CRC16En;
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reg CRC16En, next_CRC16En;
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wire [15:0] CRC16Result;
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wire [15:0] CRC16Result;
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wire CRC16UpdateRdy;
|
wire CRC16UpdateRdy;
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reg CRC5_8Bit, next_CRC5_8Bit;
|
reg CRC5En, next_CRC5En;
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reg CRC5En, next_CRC5En;
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wire [4:0] CRC5Result;
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wire [4:0] CRC5Result;
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wire CRC5UpdateRdy;
|
wire CRC5UpdateRdy;
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reg CRC5_8Bit, next_CRC5_8Bit;
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reg [7:0] CRCData, next_CRCData;
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reg [7:0] CRCData, next_CRCData;
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wire [1:0] JBit;
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wire [1:0] JBit;
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wire [1:0] KBit;
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wire [1:0] KBit;
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wire processTxByteRdy;
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reg processTxByteWEn, next_processTxByteWEn;
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wire rst;
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reg rstCRC, next_rstCRC;
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wire [7:0] SIEPortCtrlIn;
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wire [7:0] SIEPortCtrlIn;
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wire [7:0] SIEPortDataIn;
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wire [7:0] SIEPortDataIn;
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reg SIEPortTxRdy, next_SIEPortTxRdy;
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reg SIEPortTxRdy, next_SIEPortTxRdy;
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wire SIEPortWEn;
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wire SIEPortWEn;
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reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
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reg [7:0] TxByteOut, next_TxByteOut;
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reg [7:0] TxByteOut, next_TxByteOut;
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reg [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
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reg USBWireCtrl, next_USBWireCtrl;
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reg USBWireCtrl, next_USBWireCtrl;
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reg [1:0] USBWireData, next_USBWireData;
|
reg [1:0] USBWireData, next_USBWireData;
|
wire USBWireGnt;
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wire USBWireGnt;
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wire USBWireRdy;
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wire USBWireRdy;
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reg USBWireReq, next_USBWireReq;
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reg USBWireReq, next_USBWireReq;
|
reg USBWireWEn, next_USBWireWEn;
|
reg USBWireWEn, next_USBWireWEn;
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wire clk;
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wire processTxByteRdy;
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reg processTxByteWEn, next_processTxByteWEn;
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wire rst;
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reg rstCRC, next_rstCRC;
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// diagram signals declarations
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// diagram signals declarations
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reg [4:0]i, next_i;
|
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortData, next_SIEPortData;
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reg [7:0]SIEPortData, next_SIEPortData;
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reg [4:0]i, next_i;
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// BINARY ENCODED state machine: SIETx
|
// BINARY ENCODED state machine: SIETx
|
// State codes definitions:
|
// State codes definitions:
|
`define RES_ST_CHK_FIN 6'b000000
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`define DIR_CTL_CHK_FIN 6'b000000
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`define IDLE_CHK_FIN 6'b000001
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`define IDLE_CHK_FIN 6'b000001
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`define DIR_CTL_CHK_FIN 6'b000010
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`define RES_ST_CHK_FIN 6'b000010
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`define PKT_ST_CHK_PID 6'b000011
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`define PKT_ST_CHK_PID 6'b000011
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`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
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`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
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`define PKT_ST_SPCL_PKT_SENT 6'b000101
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`define PKT_ST_HS_PKT_SENT 6'b000101
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`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
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`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
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`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
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`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
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`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
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`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
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`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
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`define PKT_ST_SPCL_PKT_SENT 6'b001001
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`define PKT_ST_HS_PKT_SENT 6'b001010
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`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
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`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
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`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
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`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
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`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
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`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
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`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
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`define RES_ST_S1 6'b001110
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`define RES_ST_S1 6'b001110
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`define RES_ST_S3 6'b001111
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`define RES_ST_S3 6'b001111
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| Line 113... |
Line 143... |
`define STX_CHK_ST 6'b010111
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`define STX_CHK_ST 6'b010111
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`define STX_WAIT_BYTE 6'b011000
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`define STX_WAIT_BYTE 6'b011000
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`define IDLE_STX_WAIT_GNT 6'b011001
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`define IDLE_STX_WAIT_GNT 6'b011001
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`define IDLE_STX_WAIT_RDY 6'b011010
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`define IDLE_STX_WAIT_RDY 6'b011010
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011100
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b011101
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
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`define DIR_CTL_WAIT_GNT 6'b100001
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`define RES_ST_WAIT_GNT 6'b100001
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`define RES_ST_WAIT_GNT 6'b100010
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`define DIR_CTL_WAIT_GNT 6'b100010
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`define PKT_ST_HS_WAIT_RDY 6'b100011
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100011
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100100
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`define PKT_ST_SPCL_WAIT_RDY 6'b100101
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
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`define RES_ST_WAIT_RDY 6'b100110
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`define PKT_ST_HS_WAIT_RDY 6'b100110
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
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`define RES_ST_WAIT_RDY 6'b100111
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b101001
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
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`define PKT_ST_SPCL_WAIT_RDY 6'b101010
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`define DIR_CTL_WAIT_RDY 6'b101011
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`define DIR_CTL_WAIT_RDY 6'b101011
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
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`define PKT_ST_WAIT_RDY_PKT 6'b101110
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`define PKT_ST_WAIT_RDY_PKT 6'b101110
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`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
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`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
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| Line 139... |
Line 169... |
`define PKT_ST_WAIT_GNT 6'b110001
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`define PKT_ST_WAIT_GNT 6'b110001
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`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
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`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
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`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
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`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
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`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
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`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
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reg [5:0] CurrState_SIETx;
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reg [5:0]CurrState_SIETx, NextState_SIETx;
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reg [5:0] NextState_SIETx;
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//--------------------------------------------------------------------
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// Machine: SIETx
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// Machine: SIETx
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
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always @ (SIEPortDataIn or SIEPortCtrlIn or i or SIEPortData or JBit or CRC16Result or CRC5Result or KBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
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begin
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begin : SIETx_NextState
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NextState_SIETx <= CurrState_SIETx;
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NextState_SIETx <= CurrState_SIETx;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
|
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next_USBWireWEn <= USBWireWEn;
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next_i <= i;
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next_USBWireReq <= USBWireReq;
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next_processTxByteWEn <= processTxByteWEn;
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next_processTxByteWEn <= processTxByteWEn;
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next_TxByteOut <= TxByteOut;
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next_rstCRC <= rstCRC;
|
next_TxByteOutCtrl <= TxByteOutCtrl;
|
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next_USBWireData <= USBWireData;
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next_USBWireData <= USBWireData;
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next_USBWireCtrl <= USBWireCtrl;
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next_USBWireCtrl <= USBWireCtrl;
|
next_USBWireReq <= USBWireReq;
|
next_TxByteOut <= TxByteOut;
|
next_USBWireWEn <= USBWireWEn;
|
next_TxByteOutCtrl <= TxByteOutCtrl;
|
next_rstCRC <= rstCRC;
|
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next_CRCData <= CRCData;
|
next_CRCData <= CRCData;
|
next_CRC5En <= CRC5En;
|
next_CRC5En <= CRC5En;
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next_CRC5_8Bit <= CRC5_8Bit;
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next_CRC5_8Bit <= CRC5_8Bit;
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next_CRC16En <= CRC16En;
|
next_CRC16En <= CRC16En;
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next_SIEPortTxRdy <= SIEPortTxRdy;
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next_SIEPortTxRdy <= SIEPortTxRdy;
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next_SIEPortData <= SIEPortData;
|
next_SIEPortData <= SIEPortData;
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next_SIEPortCtrl <= SIEPortCtrl;
|
next_SIEPortCtrl <= SIEPortCtrl;
|
next_i <= i;
|
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case (CurrState_SIETx) // synopsys parallel_case full_case
|
case (CurrState_SIETx) // synopsys parallel_case full_case
|
`START_SIETX:
|
`START_SIETX:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
next_TxByteOut <= 8'h00;
|
next_TxByteOut <= 8'h00;
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| Line 191... |
Line 217... |
next_SIEPortCtrl <= 8'h00;
|
next_SIEPortCtrl <= 8'h00;
|
next_i <= 5'h0;
|
next_i <= 5'h0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`STX_CHK_ST:
|
`STX_CHK_ST:
|
|
begin
|
if (SIEPortCtrl == `TX_PACKET_START)
|
if (SIEPortCtrl == `TX_PACKET_START)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_WAIT_GNT;
|
NextState_SIETx <= `PKT_ST_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
end
|
end
|
else if (SIEPortCtrl == `TX_IDLE)
|
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
|
begin
|
begin
|
NextState_SIETx <= `IDLE_STX_WAIT_GNT;
|
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
end
|
end
|
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
|
else if (SIEPortCtrl == `TX_IDLE)
|
begin
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
|
NextState_SIETx <= `IDLE_STX_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
end
|
end
|
else if (SIEPortCtrl == `TX_RESUME_START)
|
else if (SIEPortCtrl == `TX_RESUME_START)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_GNT;
|
NextState_SIETx <= `RES_ST_WAIT_GNT;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
next_i <= 5'h0;
|
next_i <= 5'h0;
|
end
|
end
|
|
end
|
`STX_WAIT_BYTE:
|
`STX_WAIT_BYTE:
|
begin
|
begin
|
next_SIEPortTxRdy <= 1'b1;
|
next_SIEPortTxRdy <= 1'b1;
|
if (SIEPortWEn == 1'b1)
|
if (SIEPortWEn == 1'b1)
|
begin
|
begin
|
| Line 233... |
Line 261... |
begin
|
begin
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
end
|
end
|
else
|
else
|
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
end
|
end
|
|
end
|
`DIR_CTL_WAIT_GNT:
|
`DIR_CTL_WAIT_GNT:
|
begin
|
begin
|
next_i <= 5'h0;
|
next_i <= 5'h0;
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
|
begin
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
|
end
|
end
|
|
end
|
`DIR_CTL_WAIT_RDY:
|
`DIR_CTL_WAIT_RDY:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `DIR_CTL_CHK_FIN;
|
NextState_SIETx <= `DIR_CTL_CHK_FIN;
|
next_USBWireData <= SIEPortData[1:0];
|
next_USBWireData <= SIEPortData[1:0];
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
|
end
|
`IDLE_CHK_FIN:
|
`IDLE_CHK_FIN:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_i <= i + 1'b1;
|
next_i <= i + 1'b1;
|
if (i == 5'h7)
|
if (i == 5'h7)
|
begin
|
begin
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
end
|
end
|
else
|
else
|
|
begin
|
NextState_SIETx <= `IDLE_STX_WAIT_RDY;
|
NextState_SIETx <= `IDLE_STX_WAIT_RDY;
|
end
|
end
|
|
end
|
`IDLE_STX_WAIT_GNT:
|
`IDLE_STX_WAIT_GNT:
|
begin
|
begin
|
next_i <= 5'h0;
|
next_i <= 5'h0;
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
|
begin
|
NextState_SIETx <= `IDLE_STX_WAIT_RDY;
|
NextState_SIETx <= `IDLE_STX_WAIT_RDY;
|
end
|
end
|
|
end
|
`IDLE_STX_WAIT_RDY:
|
`IDLE_STX_WAIT_RDY:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `IDLE_CHK_FIN;
|
NextState_SIETx <= `IDLE_CHK_FIN;
|
next_USBWireData <= 2'b00;
|
next_USBWireData <= 2'b00;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
|
end
|
`PKT_ST_CHK_PID:
|
`PKT_ST_CHK_PID:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
if (SIEPortData[1:0] == `HANDSHAKE)
|
if (SIEPortData[1:0] == `TOKEN)
|
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
|
begin
|
else if (SIEPortData[1:0] == `TOKEN)
|
|
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
|
else if (SIEPortData[1:0] == `SPECIAL)
|
end
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
|
else if (SIEPortData[1:0] == `HANDSHAKE)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
|
|
end
|
else if (SIEPortData[1:0] == `DATA)
|
else if (SIEPortData[1:0] == `DATA)
|
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
|
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
|
end
|
end
|
|
else if (SIEPortData[1:0] == `SPECIAL)
|
|
begin
|
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
|
|
end
|
|
end
|
`PKT_ST_WAIT_RDY_PKT:
|
`PKT_ST_WAIT_RDY_PKT:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
| Line 300... |
Line 348... |
next_TxByteOut <= `SYNC_BYTE;
|
next_TxByteOut <= `SYNC_BYTE;
|
next_TxByteOutCtrl <= `DATA_START;
|
next_TxByteOutCtrl <= `DATA_START;
|
end
|
end
|
end
|
end
|
`PKT_ST_WAIT_RDY_WIRE:
|
`PKT_ST_WAIT_RDY_WIRE:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
|
//actively drive the first J bit
|
//actively drive the first J bit
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
|
end
|
`PKT_ST_WAIT_GNT:
|
`PKT_ST_WAIT_GNT:
|
|
begin
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
|
begin
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
|
NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
|
|
end
|
|
end
|
`PKT_ST_DATA_CRC_PKT_SENT1:
|
`PKT_ST_DATA_CRC_PKT_SENT1:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
|
end
|
end
|
| Line 322... |
Line 376... |
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_DATA_CRC_WAIT_RDY1:
|
`PKT_ST_DATA_CRC_WAIT_RDY1:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= ~CRC16Result[7:0];
|
next_TxByteOut <= ~CRC16Result[7:0];
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
|
end
|
`PKT_ST_DATA_CRC_WAIT_RDY2:
|
`PKT_ST_DATA_CRC_WAIT_RDY2:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= ~CRC16Result[15:8];
|
next_TxByteOut <= ~CRC16Result[15:8];
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
|
end
|
`PKT_ST_DATA_DATA_CHK_STOP:
|
`PKT_ST_DATA_DATA_CHK_STOP:
|
|
begin
|
if (SIEPortCtrl == `TX_PACKET_STOP)
|
if (SIEPortCtrl == `TX_PACKET_STOP)
|
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
|
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
|
|
end
|
else
|
else
|
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
|
|
end
|
|
end
|
`PKT_ST_DATA_DATA_PKT_SENT:
|
`PKT_ST_DATA_DATA_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
end
|
end
|
| Line 376... |
Line 440... |
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
end
|
end
|
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
|
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
|
|
begin
|
if (CRC16UpdateRdy == 1'b1)
|
if (CRC16UpdateRdy == 1'b1)
|
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
|
|
end
|
|
end
|
`PKT_ST_DATA_PID_PKT_SENT:
|
`PKT_ST_DATA_PID_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
next_rstCRC <= 1'b0;
|
next_rstCRC <= 1'b0;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_DATA_PID_WAIT_RDY:
|
`PKT_ST_DATA_PID_WAIT_RDY:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_rstCRC <= 1'b1;
|
next_rstCRC <= 1'b1;
|
end
|
end
|
|
end
|
`PKT_ST_HS_PKT_SENT:
|
`PKT_ST_HS_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_HS_WAIT_RDY:
|
`PKT_ST_HS_WAIT_RDY:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
|
end
|
`PKT_ST_SPCL_PKT_SENT:
|
`PKT_ST_SPCL_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
|
NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
|
end
|
end
|
| Line 439... |
Line 511... |
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_SPCL_WAIT_RDY:
|
`PKT_ST_SPCL_WAIT_RDY:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
|
end
|
`PKT_ST_SPCL_WAIT_WIRE:
|
`PKT_ST_SPCL_WAIT_WIRE:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
|
NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
|
end
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
`PKT_ST_TKN_BYTE1_PKT_SENT1:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
|
end
|
end
|
| Line 489... |
Line 565... |
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
end
|
end
|
end
|
end
|
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
|
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
|
|
begin
|
if (CRC5UpdateRdy == 1'b1)
|
if (CRC5UpdateRdy == 1'b1)
|
|
begin
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
|
|
end
|
|
end
|
`PKT_ST_TKN_CRC_PKT_SENT:
|
`PKT_ST_TKN_CRC_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
| Line 526... |
Line 606... |
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
|
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
|
next_TxByteOutCtrl <= `DATA_STOP;
|
next_TxByteOutCtrl <= `DATA_STOP;
|
end
|
end
|
end
|
end
|
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
|
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
|
|
begin
|
if (CRC5UpdateRdy == 1'b1)
|
if (CRC5UpdateRdy == 1'b1)
|
|
begin
|
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
|
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
|
|
end
|
|
end
|
`PKT_ST_TKN_PID_PKT_SENT:
|
`PKT_ST_TKN_PID_PKT_SENT:
|
begin
|
begin
|
next_processTxByteWEn <= 1'b0;
|
next_processTxByteWEn <= 1'b0;
|
next_rstCRC <= 1'b0;
|
next_rstCRC <= 1'b0;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
|
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
|
end
|
end
|
`PKT_ST_TKN_PID_WAIT_RDY:
|
`PKT_ST_TKN_PID_WAIT_RDY:
|
|
begin
|
if (processTxByteRdy == 1'b1)
|
if (processTxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
|
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
|
next_processTxByteWEn <= 1'b1;
|
next_processTxByteWEn <= 1'b1;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOut <= SIEPortData;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_TxByteOutCtrl <= `DATA_STREAM;
|
next_rstCRC <= 1'b1;
|
next_rstCRC <= 1'b1;
|
end
|
end
|
|
end
|
`RES_ST_CHK_FIN:
|
`RES_ST_CHK_FIN:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (i == `RESUME_LEN)
|
if (i == `RESUME_LEN)
|
|
begin
|
NextState_SIETx <= `RES_ST_S1;
|
NextState_SIETx <= `RES_ST_S1;
|
|
end
|
else
|
else
|
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
end
|
end
|
|
end
|
`RES_ST_S1:
|
`RES_ST_S1:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_S3;
|
NextState_SIETx <= `RES_ST_S3;
|
next_USBWireData <= `SE0;
|
next_USBWireData <= `SE0;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
end
|
end
|
|
end
|
`RES_ST_S3:
|
`RES_ST_S3:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
| Line 599... |
Line 691... |
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
NextState_SIETx <= `STX_WAIT_BYTE;
|
end
|
end
|
`RES_ST_WAIT_GNT:
|
`RES_ST_WAIT_GNT:
|
|
begin
|
if (USBWireGnt == 1'b1)
|
if (USBWireGnt == 1'b1)
|
|
begin
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
NextState_SIETx <= `RES_ST_WAIT_RDY;
|
|
end
|
|
end
|
`RES_ST_WAIT_RDY:
|
`RES_ST_WAIT_RDY:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
NextState_SIETx <= `RES_ST_CHK_FIN;
|
next_USBWireData <= KBit;
|
next_USBWireData <= KBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_i <= i + 1'b1;
|
next_i <= i + 1'b1;
|
end
|
end
|
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : SIETx_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_SIETx <= `START_SIETX;
|
CurrState_SIETx <= `START_SIETX;
|
else
|
else
|
CurrState_SIETx <= NextState_SIETx;
|
CurrState_SIETx <= NextState_SIETx;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : SIETx_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
SIEPortData <= 8'h00;
|
USBWireWEn <= 1'b0;
|
SIEPortCtrl <= 8'h00;
|
USBWireReq <= 1'b0;
|
i <= 5'h0;
|
|
processTxByteWEn <= 1'b0;
|
processTxByteWEn <= 1'b0;
|
TxByteOut <= 8'h00;
|
rstCRC <= 1'b0;
|
TxByteOutCtrl <= 8'h00;
|
|
USBWireData <= 2'b00;
|
USBWireData <= 2'b00;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireReq <= 1'b0;
|
TxByteOut <= 8'h00;
|
USBWireWEn <= 1'b0;
|
TxByteOutCtrl <= 8'h00;
|
rstCRC <= 1'b0;
|
|
CRCData <= 8'h00;
|
CRCData <= 8'h00;
|
CRC5En <= 1'b0;
|
CRC5En <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC5_8Bit <= 1'b0;
|
CRC16En <= 1'b0;
|
CRC16En <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
SIEPortTxRdy <= 1'b0;
|
|
i <= 5'h0;
|
|
SIEPortData <= 8'h00;
|
|
SIEPortCtrl <= 8'h00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
SIEPortData <= next_SIEPortData;
|
USBWireWEn <= next_USBWireWEn;
|
SIEPortCtrl <= next_SIEPortCtrl;
|
USBWireReq <= next_USBWireReq;
|
i <= next_i;
|
|
processTxByteWEn <= next_processTxByteWEn;
|
processTxByteWEn <= next_processTxByteWEn;
|
TxByteOut <= next_TxByteOut;
|
rstCRC <= next_rstCRC;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
|
USBWireData <= next_USBWireData;
|
USBWireData <= next_USBWireData;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireReq <= next_USBWireReq;
|
TxByteOut <= next_TxByteOut;
|
USBWireWEn <= next_USBWireWEn;
|
TxByteOutCtrl <= next_TxByteOutCtrl;
|
rstCRC <= next_rstCRC;
|
|
CRCData <= next_CRCData;
|
CRCData <= next_CRCData;
|
CRC5En <= next_CRC5En;
|
CRC5En <= next_CRC5En;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC5_8Bit <= next_CRC5_8Bit;
|
CRC16En <= next_CRC16En;
|
CRC16En <= next_CRC16En;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
SIEPortTxRdy <= next_SIEPortTxRdy;
|
|
i <= next_i;
|
|
SIEPortData <= next_SIEPortData;
|
|
SIEPortCtrl <= next_SIEPortCtrl;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
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No newline at end of file
|
