| Line 40... |
Line 40... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: SIETransmitter.v,v 1.2 2004-12-18 14:36:14 sfielding Exp $
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// $Id: SIETransmitter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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| Line 115... |
Line 115... |
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
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reg [7:0]SIEPortData, next_SIEPortData;
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reg [7:0]SIEPortData, next_SIEPortData;
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// BINARY ENCODED state machine: SIETx
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// BINARY ENCODED state machine: SIETx
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// State codes definitions:
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// State codes definitions:
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`define DIR_CTL_CHK_FIN 6'b000000
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`define RES_ST_CHK_FIN 6'b000000
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`define IDLE_CHK_FIN 6'b000001
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`define IDLE_CHK_FIN 6'b000001
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`define RES_ST_CHK_FIN 6'b000010
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`define DIR_CTL_CHK_FIN 6'b000010
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`define PKT_ST_CHK_PID 6'b000011
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`define PKT_ST_CHK_PID 6'b000011
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`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
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`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
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`define PKT_ST_HS_PKT_SENT 6'b000101
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`define PKT_ST_SPCL_PKT_SENT 6'b000101
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`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
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`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
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`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
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`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
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`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
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`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
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`define PKT_ST_SPCL_PKT_SENT 6'b001001
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`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
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`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
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`define PKT_ST_HS_PKT_SENT 6'b001010
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`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
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`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
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`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
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`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
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`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
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`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
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`define RES_ST_S1 6'b001110
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`define RES_ST_S1 6'b001110
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`define RES_ST_S3 6'b001111
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`define RES_ST_S3 6'b001111
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| Line 143... |
Line 143... |
`define STX_CHK_ST 6'b010111
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`define STX_CHK_ST 6'b010111
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`define STX_WAIT_BYTE 6'b011000
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`define STX_WAIT_BYTE 6'b011000
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`define IDLE_STX_WAIT_GNT 6'b011001
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`define IDLE_STX_WAIT_GNT 6'b011001
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`define IDLE_STX_WAIT_RDY 6'b011010
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`define IDLE_STX_WAIT_RDY 6'b011010
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
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`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011100
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
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`define PKT_ST_DATA_DATA_UPD_CRC 6'b011101
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`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
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`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
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`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
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`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
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`define RES_ST_WAIT_GNT 6'b100001
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`define DIR_CTL_WAIT_GNT 6'b100001
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`define DIR_CTL_WAIT_GNT 6'b100010
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`define RES_ST_WAIT_GNT 6'b100010
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100011
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`define PKT_ST_HS_WAIT_RDY 6'b100011
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100100
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
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`define PKT_ST_SPCL_WAIT_RDY 6'b100101
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`define PKT_ST_HS_WAIT_RDY 6'b100110
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`define RES_ST_WAIT_RDY 6'b100110
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`define RES_ST_WAIT_RDY 6'b100111
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`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
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`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
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`define PKT_ST_DATA_PID_WAIT_RDY 6'b101001
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`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
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`define PKT_ST_SPCL_WAIT_RDY 6'b101010
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`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
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`define DIR_CTL_WAIT_RDY 6'b101011
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`define DIR_CTL_WAIT_RDY 6'b101011
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
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`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
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`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
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`define PKT_ST_WAIT_RDY_PKT 6'b101110
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`define PKT_ST_WAIT_RDY_PKT 6'b101110
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`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
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`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
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| Line 175... |
Line 175... |
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// Machine: SIETx
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// Machine: SIETx
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
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always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or KBit or CRC5Result or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
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begin
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begin
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NextState_SIETx <= CurrState_SIETx;
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NextState_SIETx <= CurrState_SIETx;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_USBWireWEn <= USBWireWEn;
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next_USBWireWEn <= USBWireWEn;
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next_i <= i;
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next_i <= i;
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| Line 223... |
Line 223... |
if (SIEPortCtrl == `TX_PACKET_START)
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if (SIEPortCtrl == `TX_PACKET_START)
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begin
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begin
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NextState_SIETx <= `PKT_ST_WAIT_GNT;
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NextState_SIETx <= `PKT_ST_WAIT_GNT;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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end
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end
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else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
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else if (SIEPortCtrl == `TX_IDLE)
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begin
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begin
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NextState_SIETx <= `DIR_CTL_WAIT_GNT;
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NextState_SIETx <= `IDLE_STX_WAIT_GNT;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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end
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end
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else if (SIEPortCtrl == `TX_IDLE)
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else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
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begin
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begin
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NextState_SIETx <= `IDLE_STX_WAIT_GNT;
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NextState_SIETx <= `DIR_CTL_WAIT_GNT;
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next_USBWireReq <= 1'b1;
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next_USBWireReq <= 1'b1;
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end
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end
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else if (SIEPortCtrl == `TX_RESUME_START)
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else if (SIEPortCtrl == `TX_RESUME_START)
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begin
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begin
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NextState_SIETx <= `RES_ST_WAIT_GNT;
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NextState_SIETx <= `RES_ST_WAIT_GNT;
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| Line 318... |
Line 318... |
end
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end
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end
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end
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`PKT_ST_CHK_PID:
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`PKT_ST_CHK_PID:
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begin
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begin
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next_processTxByteWEn <= 1'b0;
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next_processTxByteWEn <= 1'b0;
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if (SIEPortData[1:0] == `TOKEN)
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if (SIEPortData[1:0] == `HANDSHAKE)
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begin
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NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
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end
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else if (SIEPortData[1:0] == `HANDSHAKE)
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begin
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begin
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NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
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NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
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end
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end
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else if (SIEPortData[1:0] == `DATA)
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else if (SIEPortData[1:0] == `TOKEN)
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begin
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begin
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NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
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NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
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end
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end
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else if (SIEPortData[1:0] == `SPECIAL)
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else if (SIEPortData[1:0] == `SPECIAL)
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begin
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begin
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NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
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NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
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end
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end
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else if (SIEPortData[1:0] == `DATA)
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begin
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NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
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end
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end
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end
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`PKT_ST_WAIT_RDY_PKT:
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`PKT_ST_WAIT_RDY_PKT:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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next_USBWireReq <= 1'b0;
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next_USBWireReq <= 1'b0;
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