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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [SIETransmitter.v] - Diff between revs 7 and 9

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Rev 7 Rev 9
Line 40... Line 40...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// $Id: SIETransmitter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
 
//
 
// CVS Revision History
 
//
 
// $Log: not supported by cvs2svn $
 
//
 
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`include "usbSerialInterfaceEngine_h.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
`include "usbConstants_h.v"
 
 
 
 
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reg  [7:0]SIEPortData, next_SIEPortData;
reg  [7:0]SIEPortData, next_SIEPortData;
 
 
// BINARY ENCODED state machine: SIETx
// BINARY ENCODED state machine: SIETx
// State codes definitions:
// State codes definitions:
`define RES_ST_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000000
`define IDLE_CHK_FIN 6'b000001
`define DIR_CTL_CHK_FIN 6'b000001
`define DIR_CTL_CHK_FIN 6'b000010
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_CHK_PID 6'b000011
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
`define IDLE 6'b000100
`define PKT_ST_SPCL_PKT_SENT 6'b000101
`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
`define PKT_ST_HS_PKT_SENT 6'b000110
`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
`define PKT_ST_SPCL_PKT_SENT 6'b001001
`define PKT_ST_HS_PKT_SENT 6'b001010
`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_S1 6'b001110
`define RES_ST_S1 6'b001110
`define RES_ST_S3 6'b001111
`define RES_ST_S3 6'b001111
Line 140... Line 134...
`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
`define START_SIETX 6'b010110
`define START_SIETX 6'b010110
`define STX_CHK_ST 6'b010111
`define STX_CHK_ST 6'b010111
`define STX_WAIT_BYTE 6'b011000
`define STX_WAIT_BYTE 6'b011000
`define IDLE_STX_WAIT_GNT 6'b011001
`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
`define IDLE_STX_WAIT_RDY 6'b011010
`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
`define RES_ST_WAIT_GNT 6'b011111
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
`define DIR_CTL_WAIT_GNT 6'b100000
`define DIR_CTL_WAIT_GNT 6'b100001
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
`define RES_ST_WAIT_GNT 6'b100010
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
`define PKT_ST_HS_WAIT_RDY 6'b100011
`define PKT_ST_SPCL_WAIT_RDY 6'b100011
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
`define PKT_ST_HS_WAIT_RDY 6'b100100
`define PKT_ST_SPCL_WAIT_RDY 6'b100101
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
`define RES_ST_WAIT_RDY 6'b100110
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
`define DIR_CTL_WAIT_RDY 6'b100111
`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
`define RES_ST_WAIT_RDY 6'b101000
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
`define DIR_CTL_WAIT_RDY 6'b101011
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
`define PKT_ST_WAIT_RDY_PKT 6'b101100
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
`define PKT_ST_WAIT_RDY_PKT 6'b101110
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
`define PKT_ST_WAIT_RDY_WIRE 6'b110000
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
`define PKT_ST_WAIT_GNT 6'b110001
 
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
 
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
 
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
 
 
 
reg [5:0]CurrState_SIETx, NextState_SIETx;
reg [5:0]CurrState_SIETx, NextState_SIETx;
 
 
 
 
// Machine: SIETx
// Machine: SIETx
 
 
// NextState logic (combinatorial)
// NextState logic (combinatorial)
always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or KBit or CRC5Result or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
begin
begin
  NextState_SIETx <= CurrState_SIETx;
  NextState_SIETx <= CurrState_SIETx;
  // Set default values for outputs and signals
  // Set default values for outputs and signals
  next_USBWireWEn <= USBWireWEn;
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_i <= i;
Line 196... Line 186...
  next_CRC16En <= CRC16En;
  next_CRC16En <= CRC16En;
  next_SIEPortTxRdy <= SIEPortTxRdy;
  next_SIEPortTxRdy <= SIEPortTxRdy;
  next_SIEPortData <= SIEPortData;
  next_SIEPortData <= SIEPortData;
  next_SIEPortCtrl <= SIEPortCtrl;
  next_SIEPortCtrl <= SIEPortCtrl;
  case (CurrState_SIETx)  // synopsys parallel_case full_case
  case (CurrState_SIETx)  // synopsys parallel_case full_case
 
    `IDLE:
 
    begin
 
      NextState_SIETx <= `STX_WAIT_BYTE;
 
    end
    `START_SIETX:
    `START_SIETX:
    begin
    begin
      next_processTxByteWEn <= 1'b0;
      next_processTxByteWEn <= 1'b0;
      next_TxByteOut <= 8'h00;
      next_TxByteOut <= 8'h00;
      next_TxByteOutCtrl <= 8'h00;
      next_TxByteOutCtrl <= 8'h00;
Line 220... Line 214...
    end
    end
    `STX_CHK_ST:
    `STX_CHK_ST:
    begin
    begin
      if (SIEPortCtrl == `TX_PACKET_START)
      if (SIEPortCtrl == `TX_PACKET_START)
      begin
      begin
        NextState_SIETx <= `PKT_ST_WAIT_GNT;
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
        next_USBWireReq <= 1'b1;
 
      end
 
      else if (SIEPortCtrl == `TX_IDLE)
 
      begin
 
        NextState_SIETx <= `IDLE_STX_WAIT_GNT;
 
        next_USBWireReq <= 1'b1;
 
      end
      end
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
      begin
      begin
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
        next_USBWireReq <= 1'b1;
        next_USBWireReq <= 1'b1;
      end
      end
 
      else if (SIEPortCtrl == `TX_IDLE)
 
      begin
 
        NextState_SIETx <= `IDLE;
 
      end
      else if (SIEPortCtrl == `TX_RESUME_START)
      else if (SIEPortCtrl == `TX_RESUME_START)
      begin
      begin
        NextState_SIETx <= `RES_ST_WAIT_GNT;
        NextState_SIETx <= `RES_ST_WAIT_GNT;
        next_USBWireReq <= 1'b1;
        next_USBWireReq <= 1'b1;
        next_i <= 5'h0;
        next_i <= 5'h0;
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        next_USBWireData <= SIEPortData[1:0];
        next_USBWireData <= SIEPortData[1:0];
        next_USBWireCtrl <= `DRIVE;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
        next_USBWireWEn <= 1'b1;
      end
      end
    end
    end
    `IDLE_CHK_FIN:
 
    begin
 
      next_USBWireWEn <= 1'b0;
 
      next_i <= i + 1'b1;
 
      if (i == 5'h7)
 
      begin
 
        NextState_SIETx <= `STX_WAIT_BYTE;
 
        next_USBWireReq <= 1'b0;
 
      end
 
      else
 
      begin
 
        NextState_SIETx <= `IDLE_STX_WAIT_RDY;
 
      end
 
    end
 
    `IDLE_STX_WAIT_GNT:
 
    begin
 
      next_i <= 5'h0;
 
      if (USBWireGnt == 1'b1)
 
      begin
 
        NextState_SIETx <= `IDLE_STX_WAIT_RDY;
 
      end
 
    end
 
    `IDLE_STX_WAIT_RDY:
 
    begin
 
      if (USBWireRdy == 1'b1)
 
      begin
 
        NextState_SIETx <= `IDLE_CHK_FIN;
 
        next_USBWireData <= 2'b00;
 
        next_USBWireCtrl <= `TRI_STATE;
 
        next_USBWireWEn <= 1'b1;
 
      end
 
    end
 
    `PKT_ST_CHK_PID:
    `PKT_ST_CHK_PID:
    begin
    begin
      next_processTxByteWEn <= 1'b0;
      next_processTxByteWEn <= 1'b0;
      if (SIEPortData[1:0] == `HANDSHAKE)
      if (SIEPortData[1:0] == `TOKEN)
      begin
 
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
 
      end
 
      else if (SIEPortData[1:0] == `TOKEN)
 
      begin
      begin
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
      end
      end
      else if (SIEPortData[1:0] == `SPECIAL)
      else if (SIEPortData[1:0] == `HANDSHAKE)
      begin
      begin
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
      end
      end
      else if (SIEPortData[1:0] == `DATA)
      else if (SIEPortData[1:0] == `DATA)
      begin
      begin
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
      end
      end
 
      else if (SIEPortData[1:0] == `SPECIAL)
 
      begin
 
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
 
      end
    end
    end
    `PKT_ST_WAIT_RDY_PKT:
    `PKT_ST_WAIT_RDY_PKT:
    begin
    begin
      next_USBWireWEn <= 1'b0;
 
      next_USBWireReq <= 1'b0;
 
      if (processTxByteRdy == 1'b1)
      if (processTxByteRdy == 1'b1)
      begin
      begin
        NextState_SIETx <= `PKT_ST_CHK_PID;
        NextState_SIETx <= `PKT_ST_CHK_PID;
        next_processTxByteWEn <= 1'b1;
        next_processTxByteWEn <= 1'b1;
        next_TxByteOut <= `SYNC_BYTE;
        next_TxByteOut <= `SYNC_BYTE;
        next_TxByteOutCtrl <= `DATA_START;
        next_TxByteOutCtrl <= `DATA_START;
      end
      end
    end
    end
    `PKT_ST_WAIT_RDY_WIRE:
 
    begin
 
      if (USBWireRdy == 1'b1)
 
      begin
 
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
 
        //actively drive the first J bit
 
        next_USBWireData <= JBit;
 
        next_USBWireCtrl <= `DRIVE;
 
        next_USBWireWEn <= 1'b1;
 
      end
 
    end
 
    `PKT_ST_WAIT_GNT:
 
    begin
 
      if (USBWireGnt == 1'b1)
 
      begin
 
        NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
 
      end
 
    end
 
    `PKT_ST_DATA_CRC_PKT_SENT1:
    `PKT_ST_DATA_CRC_PKT_SENT1:
    begin
    begin
      next_processTxByteWEn <= 1'b0;
      next_processTxByteWEn <= 1'b0;
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
    end
    end

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