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VERSION=1.19
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VERSION=1.15
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HEADER
|
HEADER
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FILE="processRxBit.asf"
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FILE="processRxBit.asf"
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FID=4094ffa4
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FID=4094ffa4
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LANGUAGE=VERILOG
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LANGUAGE=VERILOG
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ENTITY="processRxBit"
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ENTITY="processRxBit"
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FRAMES=ON
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FREEOID=256
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FREEOID=256
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"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// processrxbit\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processRxBit.asf,v 1.2 2004-12-18 14:36:15 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
|
MULTIPLEARCHSTATUS=FALSE
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|
SYNTHESISATTRIBUTES=TRUE
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|
HEADER_PARAM="AUTHOR,Steve"
|
|
HEADER_PARAM="COMPANY,Base2Designs"
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|
HEADER_PARAM="CREATIONDATE,4/9/2004"
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HEADER_PARAM="TITLE,processRxBit"
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|
END
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END
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OBJECTS
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OBJECTS
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L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
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L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
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F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
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G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
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G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
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L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
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L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
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S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
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S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
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I 12 6 0 Builtin Reset | 22728,190398
|
I 12 6 0 Builtin Reset | 22728,190398
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W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
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W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
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| Line 198... |
Line 215... |
A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 0; \nend"
|
A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit) //if current bit is a JBit, then\n RXBitStMachCurrState <= `IDLE_BIT_ST; //next state is idle\nelse //else\nbegin\n RXBitStMachCurrState <= `WAIT_RESUME_ST; //check for resume\n resumeWaitCnt <= 0; \nend"
|
S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
|
S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
|
A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
|
A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte; \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
|
W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
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W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
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W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
|
W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
|
I 175 0 2 Builtin OutPort | 78804,245816 "" ""
|
I 175 0 130 Builtin OutPort | 78804,245816 "" ""
|
L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
|
L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
|
I 173 0 2 Builtin OutPort | 79602,240762 "" ""
|
I 173 0 130 Builtin OutPort | 79602,240762 "" ""
|
L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
|
L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
|
I 171 0 2 Builtin OutPort | 78239,230321 "" ""
|
I 171 0 2 Builtin OutPort | 78239,230321 "" ""
|
L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
|
L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
|
A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
|
A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit) //line must leave KBit state for the end of resume\nbegin\n RXBitStMachCurrState <= `IDLE_BIT_ST;\n resumeDetected <= 1'b0; //clear resume detected flag\nend"
|
L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
|
L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
|
| Line 219... |
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171381,21420 174463,22458 177545,23497 178090,26035\
|
171381,21420 174463,22458 177545,23497 178090,26035\
|
178157,27576
|
178157,27576
|
W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
|
W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
|
145117,36964 157043,31068 161599,29627 166155,28187\
|
145117,36964 157043,31068 161599,29627 166155,28187\
|
172203,29500 175352,29567
|
172203,29500 175352,29567
|
A 191 9 4 TEXT "Actions" | 134636,218473 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
|
A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
|
C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
|
C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
|
I 187 0 2 Builtin InPort | 183608,259648 "" ""
|
I 187 0 2 Builtin InPort | 183608,259648 "" ""
|
L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
|
L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
|
I 185 0 3 Builtin InPort | 183608,264702 "" ""
|
I 185 0 3 Builtin InPort | 183608,264702 "" ""
|
L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
|
L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
|
I 183 0 2 Builtin InPort | 152486,239964 "" ""
|
I 183 0 130 Builtin InPort | 152486,239964 "" ""
|
L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
|
L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
|
I 181 0 2 Builtin InPort | 152486,249540 "" ""
|
I 181 0 2 Builtin InPort | 152486,249540 "" ""
|
L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
|
L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
|
I 179 0 2 Builtin InPort | 152752,245018 "" ""
|
I 179 0 130 Builtin InPort | 152752,245018 "" ""
|
L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
|
L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
|
I 177 0 2 Builtin OutPort | 78272,250604 "" ""
|
I 177 0 2 Builtin OutPort | 78272,250604 "" ""
|
L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
|
L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
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I 207 0 2 Builtin Signal | 18806,227486 "" ""
|
I 207 0 2 Builtin Signal | 18806,227486 "" ""
|
L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
|
L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
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I 205 0 2 Builtin Signal | 18834,232706 "" ""
|
I 205 0 130 Builtin Signal | 18834,232706 "" ""
|
L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
|
L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
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I 203 0 2 Builtin Signal | 18561,238021 "" ""
|
I 203 0 130 Builtin Signal | 18561,238021 "" ""
|
L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
|
L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
|
I 201 0 2 Builtin Signal | 19264,243362 "" ""
|
I 201 0 130 Builtin Signal | 19264,243362 "" ""
|
L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
|
L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
|
I 199 0 2 Builtin Signal | 18422,248742 "" ""
|
I 199 0 130 Builtin Signal | 18422,248742 "" ""
|
L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
|
L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
|
I 197 0 2 Builtin Signal | 18422,253264 "" ""
|
I 197 0 130 Builtin Signal | 18422,253264 "" ""
|
L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
|
L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
|
I 193 0 2 Builtin Signal | 18954,263638 "" ""
|
I 193 0 130 Builtin Signal | 18954,263638 "" ""
|
L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
|
L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
|
I 211 0 2 Builtin Signal | 78080,259259 "" ""
|
I 211 0 130 Builtin Signal | 78080,259259 "" ""
|
L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
|
L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
|
L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
|
L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
|
I 208 0 2 Builtin InPort | 152667,234292 "" ""
|
I 208 0 130 Builtin InPort | 152667,234292 "" ""
|
L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
|
L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
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S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
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S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
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H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
|
H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
|
I 215 214 0 Builtin Entry | 86360,167640
|
I 215 214 0 Builtin Entry | 86360,167640
|
I 216 214 0 Builtin Exit | 129540,111760
|
I 216 214 0 Builtin Exit | 129540,111760
|
