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// File : ../RTL/serialInterfaceEngine/processRxBit.v
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// Generated : 10/06/06 19:35:28
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// From : ../RTL/serialInterfaceEngine/processRxBit.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// processrxbit
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//// processrxbit
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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Line 45... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
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module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
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input clk;
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input [1:0]JBit;
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input [1:0]JBit;
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input [1:0]KBit;
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input [1:0]KBit;
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input [1:0] RxBitsIn;
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input RxWireActive;
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input clk;
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input processRxBitsWEn;
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input processRxBitsWEn;
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input processRxByteRdy;
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input processRxByteRdy;
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input rst;
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input rst;
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input [1:0]RxBitsIn;
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output [7:0] RxCtrlOut;
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input RxWireActive;
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output [7:0] RxDataOut;
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output processRxBitRdy;
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output processRxBitRdy;
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output processRxByteWEn;
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output processRxByteWEn;
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output resumeDetected;
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output resumeDetected;
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output [7:0]RxCtrlOut;
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output [7:0]RxDataOut;
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wire clk;
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wire [1:0]JBit;
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wire [1:0]JBit;
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wire [1:0]KBit;
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wire [1:0]KBit;
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wire [1:0] RxBitsIn;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [7:0] RxDataOut, next_RxDataOut;
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wire RxWireActive;
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wire clk;
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reg processRxBitRdy, next_processRxBitRdy;
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reg processRxBitRdy, next_processRxBitRdy;
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wire processRxBitsWEn;
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wire processRxBitsWEn;
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wire processRxByteRdy;
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wire processRxByteRdy;
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reg processRxByteWEn, next_processRxByteWEn;
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reg processRxByteWEn, next_processRxByteWEn;
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reg resumeDetected, next_resumeDetected;
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reg resumeDetected, next_resumeDetected;
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wire rst;
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wire rst;
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wire [1:0]RxBitsIn;
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reg [7:0]RxCtrlOut, next_RxCtrlOut;
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reg [7:0]RxDataOut, next_RxDataOut;
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wire RxWireActive;
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// diagram signals declarations
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// diagram signals declarations
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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reg [3:0]RXBitCount, next_RXBitCount;
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reg [3:0]RXBitCount, next_RXBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByte, next_RXByte;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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// BINARY ENCODED state machine: prRxBit
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// BINARY ENCODED state machine: prRxBit
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// State codes definitions:
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// State codes definitions:
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`define START 4'b0000
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`define START 4'b0000
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`define IDLE_FIRST_BIT 4'b0001
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`define IDLE_FIRST_BIT 4'b0001
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| Line 101... |
Line 106... |
`define RES_END_CHK1 4'b1011
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`define RES_END_CHK1 4'b1011
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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reg [3:0]CurrState_prRxBit, NextState_prRxBit;
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reg [3:0] CurrState_prRxBit;
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reg [3:0] NextState_prRxBit;
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//--------------------------------------------------------------------
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// Machine: prRxBit
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// Machine: prRxBit
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
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begin : prRxBit_NextState
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NextState_prRxBit <= CurrState_prRxBit;
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NextState_prRxBit <= CurrState_prRxBit;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_processRxByteWEn <= processRxByteWEn;
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next_processRxByteWEn <= processRxByteWEn;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxDataOut <= RxDataOut;
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next_RxDataOut <= RxDataOut;
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Line 133... |
next_oldRXBits <= oldRXBits;
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next_oldRXBits <= oldRXBits;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_bitStuffError <= bitStuffError;
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next_bitStuffError <= bitStuffError;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_processRxBitRdy <= processRxBitRdy;
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next_processRxBitRdy <= processRxBitRdy;
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case (CurrState_prRxBit) // synopsys parallel_case full_case
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case (CurrState_prRxBit)
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`START:
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`START:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_RxCtrlOut <= 8'h00;
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next_RxCtrlOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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Line 152... |
next_resumeWaitCnt <= 5'h0;
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next_resumeWaitCnt <= 5'h0;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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end
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end
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`WAIT_BITS:
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`WAIT_BITS:
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begin
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if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
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if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
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begin
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NextState_prRxBit <= `DATA_RX_CHK_SE0;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
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begin
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begin
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NextState_prRxBit <= `RES_RX_CHK;
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NextState_prRxBit <= `RES_RX_CHK;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
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end
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end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
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begin
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begin
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NextState_prRxBit <= `RES_END_CHK1;
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NextState_prRxBit <= `DATA_RX_CHK_SE0;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
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end
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end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
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begin
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begin
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NextState_prRxBit <= `IDLE_CHK_KBIT;
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NextState_prRxBit <= `IDLE_CHK_KBIT;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
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end
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end
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else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
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begin
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NextState_prRxBit <= `RES_END_CHK1;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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end
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end
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`IDLE_FIRST_BIT:
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`IDLE_FIRST_BIT:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
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next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
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Line 189... |
next_RXByte <= 8'h00;
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next_RXByte <= 8'h00;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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`IDLE_CHK_KBIT:
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`IDLE_CHK_KBIT:
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begin
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if ((RxBits == KBit) && (RxWireActive == 1'b1))
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if ((RxBits == KBit) && (RxWireActive == 1'b1))
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begin
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NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
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NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
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end
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else
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else
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begin
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begin
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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end
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`IDLE_WAIT_PRB_RDY:
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`IDLE_WAIT_PRB_RDY:
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begin
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if (processRxByteRdy == 1'b1)
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if (processRxByteRdy == 1'b1)
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begin
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begin
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NextState_prRxBit <= `IDLE_FIRST_BIT;
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NextState_prRxBit <= `IDLE_FIRST_BIT;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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//redundant data
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//redundant data
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next_RxCtrlOut <= `DATA_START;
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next_RxCtrlOut <= `DATA_START;
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//start of packet
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//start of packet
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next_processRxByteWEn <= 1'b1;
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next_processRxByteWEn <= 1'b1;
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end
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end
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end
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`DATA_RX_LAST_BIT:
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`DATA_RX_LAST_BIT:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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| Line 216... |
Line 217... |
end
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end
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`DATA_RX_CHK_SE0:
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`DATA_RX_CHK_SE0:
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begin
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begin
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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if (RxBits == `SE0)
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if (RxBits == `SE0)
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begin
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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end
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else
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else
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begin
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begin
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NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
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if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
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begin
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begin
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Line 236... |
if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
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if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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//early indication of ready
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//early indication of ready
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end
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end
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next_RXByte <= { 1'b1, RXByte[7:1]};
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next_RXByte <= { 1'b1, RXByte[7:1]};
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//RZ bit <= 1 (ie no change in 'RxBits')
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//RZ bit = 1 (ie no change in 'RxBits')
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end
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end
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end
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end
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else //else current 'RxBits' are different from old 'RxBits'
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else //else current 'RxBits' are different from old 'RxBits'
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begin
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begin
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if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
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if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
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| Line 250... |
Line 249... |
if (RXBitCount != 4'h7) begin
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if (RXBitCount != 4'h7) begin
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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//early indication of ready
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//early indication of ready
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end
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end
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next_RXByte <= {1'b0, RXByte[7:1]};
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next_RXByte <= {1'b0, RXByte[7:1]};
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//RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
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//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
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end
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end
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next_RXSameBitCount <= 4'h0;
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next_RXSameBitCount <= 4'h0;
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//reset 'RXSameBitCount'
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//reset 'RXSameBitCount'
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end
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end
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next_oldRXBits <= RxBits;
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next_oldRXBits <= RxBits;
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end
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end
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end
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end
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`DATA_RX_WAIT_PRB_RDY:
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`DATA_RX_WAIT_PRB_RDY:
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begin
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if (processRxByteRdy == 1'b1)
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if (processRxByteRdy == 1'b1)
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begin
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begin
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NextState_prRxBit <= `DATA_RX_LAST_BIT;
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NextState_prRxBit <= `DATA_RX_LAST_BIT;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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//redundant data
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//redundant data
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next_RxCtrlOut <= `DATA_STOP;
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next_RxCtrlOut <= `DATA_STOP;
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//end of packet
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//end of packet
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next_processRxByteWEn <= 1'b1;
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next_processRxByteWEn <= 1'b1;
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end
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end
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end
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`DATA_RX_DATA_DESTUFF:
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`DATA_RX_DATA_DESTUFF:
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begin
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if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
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if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
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begin
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NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
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NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
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end
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else if (bitStuffError == 1'b1)
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else if (bitStuffError == 1'b1)
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begin
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NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
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NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
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end
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else
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else
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begin
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begin
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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end
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`DATA_RX_BYTE_SEND2:
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`DATA_RX_BYTE_SEND2:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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`DATA_RX_BYTE_WAIT_RDY:
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`DATA_RX_BYTE_WAIT_RDY:
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begin
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if (processRxByteRdy == 1'b1)
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if (processRxByteRdy == 1'b1)
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begin
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begin
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NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
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NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
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next_RXBitCount <= 4'h0;
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next_RXBitCount <= 4'h0;
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next_RxDataOut <= RXByte;
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next_RxDataOut <= RXByte;
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next_RxCtrlOut <= `DATA_STREAM;
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next_RxCtrlOut <= `DATA_STREAM;
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next_processRxByteWEn <= 1'b1;
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next_processRxByteWEn <= 1'b1;
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end
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end
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end
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`DATA_RX_ERROR_CHK_RES:
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`DATA_RX_ERROR_CHK_RES:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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if (RxBits == JBit) //if current bit is a JBit, then
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if (RxBits == JBit) //if current bit is a JBit, then
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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| Line 319... |
Line 308... |
end
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end
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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`DATA_RX_ERROR_WAIT_RDY:
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`DATA_RX_ERROR_WAIT_RDY:
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begin
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if (processRxByteRdy == 1'b1)
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if (processRxByteRdy == 1'b1)
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begin
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begin
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NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
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NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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//redundant data
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//redundant data
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next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
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next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
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next_processRxByteWEn <= 1'b1;
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next_processRxByteWEn <= 1'b1;
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end
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end
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end
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|
`RES_RX_CHK:
|
`RES_RX_CHK:
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begin
|
begin
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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else
|
else
|
| Line 361... |
Line 348... |
next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
|
end
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end
|
endcase
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endcase
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end
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end
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|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prRxBit_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_prRxBit <= `START;
|
CurrState_prRxBit <= `START;
|
else
|
else
|
CurrState_prRxBit <= NextState_prRxBit;
|
CurrState_prRxBit <= NextState_prRxBit;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prRxBit_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
processRxByteWEn <= 1'b0;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOut <= 8'h00;
|
|
resumeDetected <= 1'b0;
|
|
processRxBitRdy <= 1'b1;
|
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RxBits <= 2'b00;
|
RxBits <= 2'b00;
|
RXSameBitCount <= 4'h0;
|
RXSameBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
oldRXBits <= 2'b00;
|
oldRXBits <= 2'b00;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
bitStuffError <= 1'b0;
|
bitStuffError <= 1'b0;
|
resumeWaitCnt <= 5'h0;
|
resumeWaitCnt <= 5'h0;
|
|
processRxByteWEn <= 1'b0;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOut <= 8'h00;
|
|
resumeDetected <= 1'b0;
|
|
processRxBitRdy <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
processRxByteWEn <= next_processRxByteWEn;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOut <= next_RxDataOut;
|
|
resumeDetected <= next_resumeDetected;
|
|
processRxBitRdy <= next_processRxBitRdy;
|
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RxBits <= next_RxBits;
|
RxBits <= next_RxBits;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXBitCount <= next_RXBitCount;
|
RXBitCount <= next_RXBitCount;
|
oldRXBits <= next_oldRXBits;
|
oldRXBits <= next_oldRXBits;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
bitStuffError <= next_bitStuffError;
|
bitStuffError <= next_bitStuffError;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
|
processRxByteWEn <= next_processRxByteWEn;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOut <= next_RxDataOut;
|
|
resumeDetected <= next_resumeDetected;
|
|
processRxBitRdy <= next_processRxBitRdy;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
