| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// processrxbit
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxBit.v
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// $Id: processRxBit.v,v 1.2 2004-12-18 14:36:15 sfielding Exp $
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// Generated : 09/12/04 22:54:47
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// From : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxBit.asf
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// By : FSM2VHDL ver. 4.0.3.8
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
|
module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
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input clk;
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input [1:0] JBit;
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input [1:0] JBit;
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input [1:0] KBit;
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input [1:0] KBit;
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input [1:0] RxBitsIn;
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input clk;
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input processRxBitsWEn;
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input processRxBitsWEn;
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input processRxByteRdy;
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input processRxByteRdy;
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input rst;
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input rst;
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output [7:0] RxCtrlOut;
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input [1:0]RxBitsIn;
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output [7:0] RxDataOut;
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output processRxBitRdy;
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output processRxBitRdy;
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output processRxByteWEn;
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output processRxByteWEn;
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output resumeDetected;
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output resumeDetected;
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output [7:0]RxCtrlOut;
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output [7:0]RxDataOut;
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wire clk;
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wire [1:0] JBit;
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wire [1:0] JBit;
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wire [1:0] KBit;
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wire [1:0] KBit;
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wire [1:0] RxBitsIn;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [7:0] RxDataOut, next_RxDataOut;
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wire clk;
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reg processRxBitRdy, next_processRxBitRdy;
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reg processRxBitRdy, next_processRxBitRdy;
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wire processRxBitsWEn;
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wire processRxBitsWEn;
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wire processRxByteRdy;
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wire processRxByteRdy;
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reg processRxByteWEn, next_processRxByteWEn;
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reg processRxByteWEn, next_processRxByteWEn;
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reg resumeDetected, next_resumeDetected;
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reg resumeDetected, next_resumeDetected;
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wire rst;
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wire rst;
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wire [1:0]RxBitsIn;
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reg [7:0]RxCtrlOut, next_RxCtrlOut;
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reg [7:0]RxDataOut, next_RxDataOut;
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// diagram signals declarations
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// diagram signals declarations
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [3:0]resumeWaitCnt, next_resumeWaitCnt;
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reg [3:0]RXBitCount, next_RXBitCount;
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reg [3:0]RXBitCount, next_RXBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByte, next_RXByte;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
|
reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [3:0]resumeWaitCnt, next_resumeWaitCnt;
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// BINARY ENCODED state machine: prRxBit
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// BINARY ENCODED state machine: prRxBit
|
// State codes definitions:
|
// State codes definitions:
|
`define START 4'b0000
|
`define START 4'b0000
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`define IDLE_FIRST_BIT 4'b0001
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`define IDLE_FIRST_BIT 4'b0001
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| Line 75... |
Line 105... |
`define RES_END_CHK1 4'b1011
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`define RES_END_CHK1 4'b1011
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define IDLE_WAIT_PRB_RDY 4'b1100
|
`define DATA_RX_WAIT_PRB_RDY 4'b1101
|
`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
|
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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reg [3:0] CurrState_prRxBit;
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reg [3:0]CurrState_prRxBit, NextState_prRxBit;
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reg [3:0] NextState_prRxBit;
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//--------------------------------------------------------------------
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// Machine: prRxBit
|
// Machine: prRxBit
|
//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
|
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
|
begin
|
begin : prRxBit_NextState
|
|
NextState_prRxBit <= CurrState_prRxBit;
|
NextState_prRxBit <= CurrState_prRxBit;
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// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_processRxByteWEn <= processRxByteWEn;
|
next_processRxByteWEn <= processRxByteWEn;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxDataOut <= RxDataOut;
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next_RxDataOut <= RxDataOut;
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| Line 121... |
Line 147... |
next_resumeWaitCnt <= 4'h0;
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next_resumeWaitCnt <= 4'h0;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
end
|
end
|
`WAIT_BITS:
|
`WAIT_BITS:
|
|
begin
|
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
|
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_CHK_SE0;
|
NextState_prRxBit <= `DATA_RX_CHK_SE0;
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next_RxBits <= RxBitsIn;
|
next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
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next_processRxBitRdy <= 1'b0;
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| Line 145... |
Line 172... |
begin
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begin
|
NextState_prRxBit <= `IDLE_CHK_KBIT;
|
NextState_prRxBit <= `IDLE_CHK_KBIT;
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next_RxBits <= RxBitsIn;
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next_RxBits <= RxBitsIn;
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next_processRxBitRdy <= 1'b0;
|
next_processRxBitRdy <= 1'b0;
|
end
|
end
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end
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`IDLE_FIRST_BIT:
|
`IDLE_FIRST_BIT:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
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next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
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next_RXSameBitCount <= 4'h1;
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next_RXSameBitCount <= 4'h1;
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| Line 158... |
Line 186... |
next_RXByte <= 8'h00;
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next_RXByte <= 8'h00;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
|
end
|
end
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`IDLE_CHK_KBIT:
|
`IDLE_CHK_KBIT:
|
|
begin
|
if (RxBits == KBit)
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if (RxBits == KBit)
|
|
begin
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NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
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NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
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|
end
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else
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else
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begin
|
begin
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
|
end
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end
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|
end
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`IDLE_WAIT_PRB_RDY:
|
`IDLE_WAIT_PRB_RDY:
|
|
begin
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if (processRxByteRdy == 1'b1)
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if (processRxByteRdy == 1'b1)
|
begin
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begin
|
NextState_prRxBit <= `IDLE_FIRST_BIT;
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NextState_prRxBit <= `IDLE_FIRST_BIT;
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next_RxDataOut <= 8'h00;
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next_RxDataOut <= 8'h00;
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//redundant data
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//redundant data
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next_RxCtrlOut <= `DATA_START;
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next_RxCtrlOut <= `DATA_START;
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//start of packet
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//start of packet
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next_processRxByteWEn <= 1'b1;
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next_processRxByteWEn <= 1'b1;
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end
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end
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end
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`DATA_RX_LAST_BIT:
|
`DATA_RX_LAST_BIT:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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| Line 186... |
Line 220... |
end
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end
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`DATA_RX_CHK_SE0:
|
`DATA_RX_CHK_SE0:
|
begin
|
begin
|
next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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if (RxBits == `SE0)
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if (RxBits == `SE0)
|
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begin
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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end
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else
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else
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
|
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
|
if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
|
begin
|
begin
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| Line 205... |
Line 241... |
if (RXBitCount != 4'h7) begin
|
if (RXBitCount != 4'h7) begin
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
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//early indication of ready
|
//early indication of ready
|
end
|
end
|
next_RXByte <= { 1'b1, RXByte[7:1]};
|
next_RXByte <= { 1'b1, RXByte[7:1]};
|
//RZ bit = 1 (ie no change in 'RxBits')
|
//RZ bit <= 1 (ie no change in 'RxBits')
|
end
|
end
|
end
|
end
|
else //else current 'RxBits' are different from old 'RxBits'
|
else //else current 'RxBits' are different from old 'RxBits'
|
begin
|
begin
|
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
|
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
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| Line 218... |
Line 254... |
if (RXBitCount != 4'h7) begin
|
if (RXBitCount != 4'h7) begin
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
//early indication of ready
|
//early indication of ready
|
end
|
end
|
next_RXByte <= {1'b0, RXByte[7:1]};
|
next_RXByte <= {1'b0, RXByte[7:1]};
|
//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
|
//RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
|
end
|
end
|
next_RXSameBitCount <= 4'h1;
|
next_RXSameBitCount <= 4'h1;
|
//reset 'RXSameBitCount'
|
//reset 'RXSameBitCount'
|
end
|
end
|
next_oldRXBits <= RxBits;
|
next_oldRXBits <= RxBits;
|
end
|
end
|
end
|
end
|
`DATA_RX_WAIT_PRB_RDY:
|
`DATA_RX_WAIT_PRB_RDY:
|
|
begin
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_LAST_BIT;
|
NextState_prRxBit <= `DATA_RX_LAST_BIT;
|
next_RxDataOut <= 8'h00;
|
next_RxDataOut <= 8'h00;
|
//redundant data
|
//redundant data
|
next_RxCtrlOut <= `DATA_STOP;
|
next_RxCtrlOut <= `DATA_STOP;
|
//end of packet
|
//end of packet
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
|
end
|
`DATA_RX_DATA_DESTUFF:
|
`DATA_RX_DATA_DESTUFF:
|
|
begin
|
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
|
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
|
|
begin
|
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
|
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
|
|
end
|
else if (bitStuffError == 1'b1)
|
else if (bitStuffError == 1'b1)
|
|
begin
|
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
|
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
|
|
end
|
else
|
else
|
begin
|
begin
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
|
end
|
`DATA_RX_BYTE_SEND2:
|
`DATA_RX_BYTE_SEND2:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_BYTE_WAIT_RDY:
|
`DATA_RX_BYTE_WAIT_RDY:
|
|
begin
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
|
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
|
next_RXBitCount <= 4'h0;
|
next_RXBitCount <= 4'h0;
|
next_RxDataOut <= RXByte;
|
next_RxDataOut <= RXByte;
|
next_RxCtrlOut <= `DATA_STREAM;
|
next_RxCtrlOut <= `DATA_STREAM;
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
|
end
|
`DATA_RX_ERROR_CHK_RES:
|
`DATA_RX_ERROR_CHK_RES:
|
begin
|
begin
|
next_processRxByteWEn <= 1'b0;
|
next_processRxByteWEn <= 1'b0;
|
if (RxBits == JBit) //if current bit is a JBit, then
|
if (RxBits == JBit) //if current bit is a JBit, then
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
| Line 277... |
Line 323... |
end
|
end
|
NextState_prRxBit <= `WAIT_BITS;
|
NextState_prRxBit <= `WAIT_BITS;
|
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
`DATA_RX_ERROR_WAIT_RDY:
|
`DATA_RX_ERROR_WAIT_RDY:
|
|
begin
|
if (processRxByteRdy == 1'b1)
|
if (processRxByteRdy == 1'b1)
|
begin
|
begin
|
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
|
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
|
next_RxDataOut <= 8'h00;
|
next_RxDataOut <= 8'h00;
|
//redundant data
|
//redundant data
|
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
|
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
|
next_processRxByteWEn <= 1'b1;
|
next_processRxByteWEn <= 1'b1;
|
end
|
end
|
|
end
|
`RES_RX_CHK:
|
`RES_RX_CHK:
|
begin
|
begin
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
|
else
|
else
|
| Line 317... |
Line 365... |
next_processRxBitRdy <= 1'b1;
|
next_processRxBitRdy <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prRxBit_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_prRxBit <= `START;
|
CurrState_prRxBit <= `START;
|
else
|
else
|
CurrState_prRxBit <= NextState_prRxBit;
|
CurrState_prRxBit <= NextState_prRxBit;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : prRxBit_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
|
processRxByteWEn <= 1'b0;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOut <= 8'h00;
|
|
resumeDetected <= 1'b0;
|
|
processRxBitRdy <= 1'b1;
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RXBitStMachCurrState <= `IDLE_BIT_ST;
|
RxBits <= 2'b00;
|
RxBits <= 2'b00;
|
RXSameBitCount <= 4'h0;
|
RXSameBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
RXBitCount <= 4'h0;
|
oldRXBits <= 2'b00;
|
oldRXBits <= 2'b00;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
bitStuffError <= 1'b0;
|
bitStuffError <= 1'b0;
|
resumeWaitCnt <= 4'h0;
|
resumeWaitCnt <= 4'h0;
|
processRxByteWEn <= 1'b0;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOut <= 8'h00;
|
|
resumeDetected <= 1'b0;
|
|
processRxBitRdy <= 1'b1;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
processRxByteWEn <= next_processRxByteWEn;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOut <= next_RxDataOut;
|
|
resumeDetected <= next_resumeDetected;
|
|
processRxBitRdy <= next_processRxBitRdy;
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RXBitStMachCurrState <= next_RXBitStMachCurrState;
|
RxBits <= next_RxBits;
|
RxBits <= next_RxBits;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXSameBitCount <= next_RXSameBitCount;
|
RXBitCount <= next_RXBitCount;
|
RXBitCount <= next_RXBitCount;
|
oldRXBits <= next_oldRXBits;
|
oldRXBits <= next_oldRXBits;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
bitStuffError <= next_bitStuffError;
|
bitStuffError <= next_bitStuffError;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
resumeWaitCnt <= next_resumeWaitCnt;
|
processRxByteWEn <= next_processRxByteWEn;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOut <= next_RxDataOut;
|
|
resumeDetected <= next_resumeDetected;
|
|
processRxBitRdy <= next_processRxBitRdy;
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
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No newline at end of file
|
