| Line 1... |
Line 1... |
|
|
|
// File : ../RTL/serialInterfaceEngine/processRxByte.v
|
|
// Generated : 10/06/06 19:35:29
|
|
// From : ../RTL/serialInterfaceEngine/processRxByte.asf
|
|
// By : FSM2VHDL ver. 5.0.0.9
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// processRxByte
|
//// processRxByte
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
| Line 40... |
Line 45... |
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`timescale 1ns / 1ps
|
`include "timescale.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
|
|
module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
|
module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
|
input clk;
|
|
input [15:0]CRC16Result;
|
input [15:0]CRC16Result;
|
input CRC16UpdateRdy;
|
input CRC16UpdateRdy;
|
input [4:0]CRC5Result;
|
input [4:0]CRC5Result;
|
input CRC5UpdateRdy;
|
input CRC5UpdateRdy;
|
input processRxDataInWEn;
|
|
input rst;
|
|
input [7:0]RxByteIn;
|
input [7:0]RxByteIn;
|
input [7:0]RxCtrlIn;
|
input [7:0]RxCtrlIn;
|
|
input clk;
|
|
input processRxDataInWEn;
|
|
input rst;
|
output CRC16En;
|
output CRC16En;
|
output CRC5_8Bit;
|
|
output CRC5En;
|
output CRC5En;
|
|
output CRC5_8Bit;
|
output [7:0]CRCData;
|
output [7:0]CRCData;
|
output processRxByteRdy;
|
|
output rstCRC;
|
|
output [7:0]RxCtrlOut;
|
output [7:0]RxCtrlOut;
|
output [7:0]RxDataOut;
|
|
output RxDataOutWEn;
|
output RxDataOutWEn;
|
|
output [7:0] RxDataOut;
|
|
output processRxByteRdy;
|
|
output rstCRC;
|
|
|
wire clk;
|
|
reg CRC16En, next_CRC16En;
|
reg CRC16En, next_CRC16En;
|
wire [15:0]CRC16Result;
|
wire [15:0]CRC16Result;
|
wire CRC16UpdateRdy;
|
wire CRC16UpdateRdy;
|
reg CRC5_8Bit, next_CRC5_8Bit;
|
|
reg CRC5En, next_CRC5En;
|
reg CRC5En, next_CRC5En;
|
wire [4:0]CRC5Result;
|
wire [4:0]CRC5Result;
|
wire CRC5UpdateRdy;
|
wire CRC5UpdateRdy;
|
|
reg CRC5_8Bit, next_CRC5_8Bit;
|
reg [7:0]CRCData, next_CRCData;
|
reg [7:0]CRCData, next_CRCData;
|
reg processRxByteRdy, next_processRxByteRdy;
|
|
wire processRxDataInWEn;
|
|
wire rst;
|
|
reg rstCRC, next_rstCRC;
|
|
wire [7:0]RxByteIn;
|
wire [7:0]RxByteIn;
|
wire [7:0]RxCtrlIn;
|
wire [7:0]RxCtrlIn;
|
reg [7:0]RxCtrlOut, next_RxCtrlOut;
|
reg [7:0]RxCtrlOut, next_RxCtrlOut;
|
reg [7:0]RxDataOut, next_RxDataOut;
|
|
reg RxDataOutWEn, next_RxDataOutWEn;
|
reg RxDataOutWEn, next_RxDataOutWEn;
|
|
reg [7:0] RxDataOut, next_RxDataOut;
|
|
wire clk;
|
|
reg processRxByteRdy, next_processRxByteRdy;
|
|
wire processRxDataInWEn;
|
|
wire rst;
|
|
reg rstCRC, next_rstCRC;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg ACKRxed, next_ACKRxed;
|
reg ACKRxed, next_ACKRxed;
|
reg bitStuffError, next_bitStuffError;
|
|
reg CRCError, next_CRCError;
|
reg CRCError, next_CRCError;
|
reg dataSequence, next_dataSequence;
|
|
reg NAKRxed, next_NAKRxed;
|
reg NAKRxed, next_NAKRxed;
|
reg [7:0]RxByte, next_RxByte;
|
|
reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
|
reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
|
reg [7:0]RxCtrl, next_RxCtrl;
|
|
reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
|
reg [9:0]RXDataByteCnt, next_RXDataByteCnt;
|
|
reg [7:0]RxByte, next_RxByte;
|
|
reg [7:0]RxCtrl, next_RxCtrl;
|
reg RxOverflow, next_RxOverflow;
|
reg RxOverflow, next_RxOverflow;
|
reg [7:0]RxStatus;
|
reg [7:0]RxStatus;
|
reg RxTimeOut, next_RxTimeOut;
|
reg RxTimeOut, next_RxTimeOut;
|
reg Signal1, next_Signal1;
|
reg Signal1, next_Signal1;
|
|
reg bitStuffError, next_bitStuffError;
|
|
reg dataSequence, next_dataSequence;
|
reg stallRxed, next_stallRxed;
|
reg stallRxed, next_stallRxed;
|
|
|
// BINARY ENCODED state machine: prRxByte
|
// BINARY ENCODED state machine: prRxByte
|
// State codes definitions:
|
// State codes definitions:
|
`define CHK_ST 4'b0000
|
`define CHK_ST 4'b0000
|
| Line 117... |
Line 122... |
`define DATA_FIN 4'b1011
|
`define DATA_FIN 4'b1011
|
`define DATA_CHK_STRM 4'b1100
|
`define DATA_CHK_STRM 4'b1100
|
`define TOKEN_WAIT_CRC 4'b1101
|
`define TOKEN_WAIT_CRC 4'b1101
|
`define DATA_WAIT_CRC 4'b1110
|
`define DATA_WAIT_CRC 4'b1110
|
|
|
reg [3:0]CurrState_prRxByte, NextState_prRxByte;
|
reg [3:0] CurrState_prRxByte;
|
|
reg [3:0] NextState_prRxByte;
|
|
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
|
|
always @
|
always @
|
(next_CRCError or next_bitStuffError or
|
(next_CRCError or next_bitStuffError or
|
next_RxOverflow or next_NAKRxed or
|
next_RxOverflow or next_NAKRxed or
|
next_stallRxed or next_ACKRxed or
|
next_stallRxed or next_ACKRxed or
|
next_dataSequence)
|
next_dataSequence)
|
| Line 134... |
Line 141... |
next_stallRxed, next_NAKRxed,
|
next_stallRxed, next_NAKRxed,
|
next_RxOverflow,
|
next_RxOverflow,
|
next_bitStuffError, next_CRCError };
|
next_bitStuffError, next_CRCError };
|
end
|
end
|
|
|
|
//--------------------------------------------------------------------
|
// Machine: prRxByte
|
// Machine: prRxByte
|
|
//--------------------------------------------------------------------
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
|
// Next State Logic (combinatorial)
|
begin
|
//----------------------------------
|
|
always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
|
|
begin : prRxByte_NextState
|
NextState_prRxByte <= CurrState_prRxByte;
|
NextState_prRxByte <= CurrState_prRxByte;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_RxByte <= RxByte;
|
next_RxByte <= RxByte;
|
next_RxCtrl <= RxCtrl;
|
next_RxCtrl <= RxCtrl;
|
next_RXByteStMachCurrState <= RXByteStMachCurrState;
|
next_RXByteStMachCurrState <= RXByteStMachCurrState;
|
| Line 163... |
Line 172... |
next_CRC5En <= CRC5En;
|
next_CRC5En <= CRC5En;
|
next_CRC5_8Bit <= CRC5_8Bit;
|
next_CRC5_8Bit <= CRC5_8Bit;
|
next_CRC16En <= CRC16En;
|
next_CRC16En <= CRC16En;
|
next_RXDataByteCnt <= RXDataByteCnt;
|
next_RXDataByteCnt <= RXDataByteCnt;
|
next_processRxByteRdy <= processRxByteRdy;
|
next_processRxByteRdy <= processRxByteRdy;
|
case (CurrState_prRxByte) // synopsys parallel_case full_case
|
case (CurrState_prRxByte)
|
`CHK_ST:
|
`CHK_ST:
|
begin
|
|
if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
|
if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
|
begin
|
|
NextState_prRxByte <= `TOKEN_WAIT_CRC;
|
NextState_prRxByte <= `TOKEN_WAIT_CRC;
|
end
|
|
else if (RXByteStMachCurrState == `HS_BYTE_ST)
|
else if (RXByteStMachCurrState == `HS_BYTE_ST)
|
begin
|
|
NextState_prRxByte <= `HSHAKE_CHK;
|
NextState_prRxByte <= `HSHAKE_CHK;
|
end
|
|
else if (RXByteStMachCurrState == `CHECK_PID_ST)
|
else if (RXByteStMachCurrState == `CHECK_PID_ST)
|
begin
|
|
NextState_prRxByte <= `CHK_PID_DO_CHK;
|
NextState_prRxByte <= `CHK_PID_DO_CHK;
|
end
|
|
else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
|
else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
|
begin
|
|
NextState_prRxByte <= `CHK_SYNC_DO;
|
NextState_prRxByte <= `CHK_SYNC_DO;
|
end
|
|
else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
|
else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
|
begin
|
|
NextState_prRxByte <= `IDLE_CHK_START;
|
NextState_prRxByte <= `IDLE_CHK_START;
|
end
|
|
else if (RXByteStMachCurrState == `DATA_BYTE_ST)
|
else if (RXByteStMachCurrState == `DATA_BYTE_ST)
|
begin
|
|
NextState_prRxByte <= `DATA_WAIT_CRC;
|
NextState_prRxByte <= `DATA_WAIT_CRC;
|
end
|
|
end
|
|
`START_PRBY:
|
`START_PRBY:
|
begin
|
begin
|
next_RxByte <= 8'h00;
|
next_RxByte <= 8'h00;
|
next_RxCtrl <= 8'h00;
|
next_RxCtrl <= 8'h00;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
| Line 217... |
Line 212... |
next_RXDataByteCnt <= 10'h00;
|
next_RXDataByteCnt <= 10'h00;
|
next_processRxByteRdy <= 1'b1;
|
next_processRxByteRdy <= 1'b1;
|
NextState_prRxByte <= `WAIT_BYTE;
|
NextState_prRxByte <= `WAIT_BYTE;
|
end
|
end
|
`WAIT_BYTE:
|
`WAIT_BYTE:
|
begin
|
|
if (processRxDataInWEn == 1'b1)
|
if (processRxDataInWEn == 1'b1)
|
begin
|
begin
|
NextState_prRxByte <= `CHK_ST;
|
NextState_prRxByte <= `CHK_ST;
|
next_RxByte <= RxByteIn;
|
next_RxByte <= RxByteIn;
|
next_RxCtrl <= RxCtrlIn;
|
next_RxCtrl <= RxCtrlIn;
|
next_processRxByteRdy <= 1'b0;
|
next_processRxByteRdy <= 1'b0;
|
end
|
end
|
end
|
|
`HSHAKE_FIN:
|
`HSHAKE_FIN:
|
begin
|
begin
|
next_RxDataOutWEn <= 1'b0;
|
next_RxDataOutWEn <= 1'b0;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
NextState_prRxByte <= `WAIT_BYTE;
|
NextState_prRxByte <= `WAIT_BYTE;
|
| Line 243... |
Line 236... |
next_RxDataOut <= RxStatus;
|
next_RxDataOut <= RxStatus;
|
next_RxCtrlOut <= `RX_PACKET_STOP;
|
next_RxCtrlOut <= `RX_PACKET_STOP;
|
next_RxDataOutWEn <= 1'b1;
|
next_RxDataOutWEn <= 1'b1;
|
end
|
end
|
`CHK_PID_DO_CHK:
|
`CHK_PID_DO_CHK:
|
begin
|
|
if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
|
if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
|
begin
|
begin
|
NextState_prRxByte <= `WAIT_BYTE;
|
NextState_prRxByte <= `WAIT_BYTE;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
next_processRxByteRdy <= 1'b1;
|
next_processRxByteRdy <= 1'b1;
|
| Line 267... |
Line 259... |
next_RxDataOut <= RxByte;
|
next_RxDataOut <= RxByte;
|
next_RxCtrlOut <= `RX_PACKET_START;
|
next_RxCtrlOut <= `RX_PACKET_START;
|
next_RxDataOutWEn <= 1'b1;
|
next_RxDataOutWEn <= 1'b1;
|
next_rstCRC <= 1'b1;
|
next_rstCRC <= 1'b1;
|
end
|
end
|
end
|
|
`CHK_PID_FIRST_BYTE_PROC:
|
`CHK_PID_FIRST_BYTE_PROC:
|
begin
|
begin
|
next_rstCRC <= 1'b0;
|
next_rstCRC <= 1'b0;
|
next_RxDataOutWEn <= 1'b0;
|
next_RxDataOutWEn <= 1'b0;
|
case (RxByte[1:0] )
|
case (RxByte[1:0] )
|
| Line 346... |
Line 337... |
next_RxDataOut <= RxByte;
|
next_RxDataOut <= RxByte;
|
next_RxCtrlOut <= `RX_PACKET_STREAM;
|
next_RxCtrlOut <= `RX_PACKET_STREAM;
|
next_CRCData <= RxByte;
|
next_CRCData <= RxByte;
|
next_CRC16En <= 1'b1;
|
next_CRC16En <= 1'b1;
|
end
|
end
|
|
default:
|
|
begin
|
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
|
end
|
endcase
|
endcase
|
next_RxDataOutWEn <= 1'b1;
|
next_RxDataOutWEn <= 1'b1;
|
NextState_prRxByte <= `DATA_FIN;
|
NextState_prRxByte <= `DATA_FIN;
|
end
|
end
|
`DATA_WAIT_CRC:
|
`DATA_WAIT_CRC:
|
begin
|
|
if (CRC16UpdateRdy == 1'b1)
|
if (CRC16UpdateRdy == 1'b1)
|
begin
|
|
NextState_prRxByte <= `DATA_CHK_STRM;
|
NextState_prRxByte <= `DATA_CHK_STRM;
|
end
|
|
end
|
|
`TOKEN_CHK_STRM:
|
`TOKEN_CHK_STRM:
|
begin
|
begin
|
next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
|
next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
|
case (RxCtrl)
|
case (RxCtrl)
|
`DATA_STOP:
|
`DATA_STOP:
|
| Line 394... |
Line 385... |
next_CRCData <= RxByte;
|
next_CRCData <= RxByte;
|
next_CRC5_8Bit <= 1'b1;
|
next_CRC5_8Bit <= 1'b1;
|
next_CRC5En <= 1'b1;
|
next_CRC5En <= 1'b1;
|
end
|
end
|
end
|
end
|
|
default:
|
|
begin
|
|
next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
|
end
|
endcase
|
endcase
|
next_RxDataOutWEn <= 1'b1;
|
next_RxDataOutWEn <= 1'b1;
|
NextState_prRxByte <= `TOKEN_FIN;
|
NextState_prRxByte <= `TOKEN_FIN;
|
end
|
end
|
`TOKEN_FIN:
|
`TOKEN_FIN:
|
| Line 406... |
Line 401... |
next_RxDataOutWEn <= 1'b0;
|
next_RxDataOutWEn <= 1'b0;
|
NextState_prRxByte <= `WAIT_BYTE;
|
NextState_prRxByte <= `WAIT_BYTE;
|
next_processRxByteRdy <= 1'b1;
|
next_processRxByteRdy <= 1'b1;
|
end
|
end
|
`TOKEN_WAIT_CRC:
|
`TOKEN_WAIT_CRC:
|
begin
|
|
if (CRC5UpdateRdy == 1'b1)
|
if (CRC5UpdateRdy == 1'b1)
|
begin
|
|
NextState_prRxByte <= `TOKEN_CHK_STRM;
|
NextState_prRxByte <= `TOKEN_CHK_STRM;
|
end
|
|
end
|
|
`CHK_SYNC_DO:
|
`CHK_SYNC_DO:
|
begin
|
begin
|
if (RxByte == `SYNC_BYTE)
|
if (RxByte == `SYNC_BYTE)
|
next_RXByteStMachCurrState <= `CHECK_PID_ST;
|
next_RXByteStMachCurrState <= `CHECK_PID_ST;
|
else
|
else
|
| Line 431... |
Line 422... |
next_processRxByteRdy <= 1'b1;
|
next_processRxByteRdy <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prRxByte_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_prRxByte <= `START_PRBY;
|
CurrState_prRxByte <= `START_PRBY;
|
else
|
else
|
CurrState_prRxByte <= NextState_prRxByte;
|
CurrState_prRxByte <= NextState_prRxByte;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prRxByte_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RxDataOut <= 8'h00;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOutWEn <= 1'b0;
|
|
rstCRC <= 1'b0;
|
|
CRCData <= 8'h00;
|
|
CRC5En <= 1'b0;
|
|
CRC5_8Bit <= 1'b0;
|
|
CRC16En <= 1'b0;
|
|
processRxByteRdy <= 1'b1;
|
|
RxByte <= 8'h00;
|
RxByte <= 8'h00;
|
RxCtrl <= 8'h00;
|
RxCtrl <= 8'h00;
|
RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
RXByteStMachCurrState <= `IDLE_BYTE_ST;
|
CRCError <= 1'b0;
|
CRCError <= 1'b0;
|
bitStuffError <= 1'b0;
|
bitStuffError <= 1'b0;
|
| Line 466... |
Line 452... |
NAKRxed <= 1'b0;
|
NAKRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
stallRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
dataSequence <= 1'b0;
|
dataSequence <= 1'b0;
|
RXDataByteCnt <= 10'h00;
|
RXDataByteCnt <= 10'h00;
|
|
RxDataOut <= 8'h00;
|
|
RxCtrlOut <= 8'h00;
|
|
RxDataOutWEn <= 1'b0;
|
|
rstCRC <= 1'b0;
|
|
CRCData <= 8'h00;
|
|
CRC5En <= 1'b0;
|
|
CRC5_8Bit <= 1'b0;
|
|
CRC16En <= 1'b0;
|
|
processRxByteRdy <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxDataOut <= next_RxDataOut;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOutWEn <= next_RxDataOutWEn;
|
|
rstCRC <= next_rstCRC;
|
|
CRCData <= next_CRCData;
|
|
CRC5En <= next_CRC5En;
|
|
CRC5_8Bit <= next_CRC5_8Bit;
|
|
CRC16En <= next_CRC16En;
|
|
processRxByteRdy <= next_processRxByteRdy;
|
|
RxByte <= next_RxByte;
|
RxByte <= next_RxByte;
|
RxCtrl <= next_RxCtrl;
|
RxCtrl <= next_RxCtrl;
|
RXByteStMachCurrState <= next_RXByteStMachCurrState;
|
RXByteStMachCurrState <= next_RXByteStMachCurrState;
|
CRCError <= next_CRCError;
|
CRCError <= next_CRCError;
|
bitStuffError <= next_bitStuffError;
|
bitStuffError <= next_bitStuffError;
|
| Line 490... |
Line 476... |
NAKRxed <= next_NAKRxed;
|
NAKRxed <= next_NAKRxed;
|
stallRxed <= next_stallRxed;
|
stallRxed <= next_stallRxed;
|
ACKRxed <= next_ACKRxed;
|
ACKRxed <= next_ACKRxed;
|
dataSequence <= next_dataSequence;
|
dataSequence <= next_dataSequence;
|
RXDataByteCnt <= next_RXDataByteCnt;
|
RXDataByteCnt <= next_RXDataByteCnt;
|
|
RxDataOut <= next_RxDataOut;
|
|
RxCtrlOut <= next_RxCtrlOut;
|
|
RxDataOutWEn <= next_RxDataOutWEn;
|
|
rstCRC <= next_rstCRC;
|
|
CRCData <= next_CRCData;
|
|
CRC5En <= next_CRC5En;
|
|
CRC5_8Bit <= next_CRC5_8Bit;
|
|
CRC16En <= next_CRC16En;
|
|
processRxByteRdy <= next_processRxByteRdy;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
