| Line 44... |
Line 44... |
//
|
//
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
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|
|
module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
|
module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
|
input clk;
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input clk;
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input fullSpeedRate;
|
|
input [1:0]JBit;
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input [1:0]JBit;
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input [1:0]KBit;
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input [1:0]KBit;
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input processTxByteWEn;
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input processTxByteWEn;
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input rst;
|
input rst;
|
input [7:0]TxByteCtrlIn;
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input [7:0]TxByteCtrlIn;
|
|
input TxByteFullSpeedRateIn;
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input [7:0]TxByteIn;
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input [7:0]TxByteIn;
|
input USBWireGnt;
|
input USBWireGnt;
|
input USBWireRdy;
|
input USBWireRdy;
|
output processTxByteRdy;
|
output processTxByteRdy;
|
output USBWireCtrl;
|
output USBWireCtrl;
|
output [1:0]USBWireData;
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output [1:0]USBWireData;
|
|
output USBWireFullSpeedRate;
|
output USBWireReq;
|
output USBWireReq;
|
output USBWireWEn;
|
output USBWireWEn;
|
|
|
wire clk;
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wire clk;
|
wire fullSpeedRate;
|
|
wire [1:0]JBit;
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wire [1:0]JBit;
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wire [1:0]KBit;
|
wire [1:0]KBit;
|
reg processTxByteRdy, next_processTxByteRdy;
|
reg processTxByteRdy, next_processTxByteRdy;
|
wire processTxByteWEn;
|
wire processTxByteWEn;
|
wire rst;
|
wire rst;
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wire [7:0]TxByteCtrlIn;
|
wire [7:0]TxByteCtrlIn;
|
|
wire TxByteFullSpeedRateIn;
|
wire [7:0]TxByteIn;
|
wire [7:0]TxByteIn;
|
reg USBWireCtrl, next_USBWireCtrl;
|
reg USBWireCtrl, next_USBWireCtrl;
|
reg [1:0]USBWireData, next_USBWireData;
|
reg [1:0]USBWireData, next_USBWireData;
|
|
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
|
wire USBWireGnt;
|
wire USBWireGnt;
|
wire USBWireRdy;
|
wire USBWireRdy;
|
reg USBWireReq, next_USBWireReq;
|
reg USBWireReq, next_USBWireReq;
|
reg USBWireWEn, next_USBWireWEn;
|
reg USBWireWEn, next_USBWireWEn;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [3:0]i, next_i;
|
reg [3:0]i, next_i;
|
reg [7:0]TxByte, next_TxByte;
|
reg [7:0]TxByte, next_TxByte;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
|
|
reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
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reg [1:0]TXLineState, next_TXLineState;
|
reg [1:0]TXLineState, next_TXLineState;
|
reg [3:0]TXOneCount, next_TXOneCount;
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reg [3:0]TXOneCount, next_TXOneCount;
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|
|
// BINARY ENCODED state machine: prcTxB
|
// BINARY ENCODED state machine: prcTxB
|
// State codes definitions:
|
// State codes definitions:
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| Line 108... |
Line 111... |
`define LS_START_SND_IDLE3 5'b10001
|
`define LS_START_SND_IDLE3 5'b10001
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`define LS_START_SND_J1 5'b10010
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`define LS_START_SND_J1 5'b10010
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`define LS_START_SND_IDLE1 5'b10011
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`define LS_START_SND_IDLE1 5'b10011
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`define LS_START_SND_IDLE2 5'b10100
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`define LS_START_SND_IDLE2 5'b10100
|
`define LS_START_FIN 5'b10101
|
`define LS_START_FIN 5'b10101
|
|
`define LS_START_W_RDY1 5'b10110
|
|
`define LS_START_W_RDY2 5'b10111
|
|
`define LS_START_W_RDY3 5'b11000
|
|
`define STOP_W_RDY1 5'b11001
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|
`define STOP_W_RDY2 5'b11010
|
|
`define STOP_W_RDY3 5'b11011
|
|
`define STOP_W_RDY4 5'b11100
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|
|
reg [4:0]CurrState_prcTxB, NextState_prcTxB;
|
reg [4:0]CurrState_prcTxB, NextState_prcTxB;
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|
|
|
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// Machine: prcTxB
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// Machine: prcTxB
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|
|
// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
|
always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
|
begin
|
begin
|
NextState_prcTxB <= CurrState_prcTxB;
|
NextState_prcTxB <= CurrState_prcTxB;
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// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_processTxByteRdy <= processTxByteRdy;
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next_processTxByteRdy <= processTxByteRdy;
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next_USBWireData <= USBWireData;
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next_USBWireData <= USBWireData;
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| Line 129... |
Line 139... |
next_i <= i;
|
next_i <= i;
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next_TxByte <= TxByte;
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next_TxByte <= TxByte;
|
next_TxByteCtrl <= TxByteCtrl;
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next_TxByteCtrl <= TxByteCtrl;
|
next_TXLineState <= TXLineState;
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next_TXLineState <= TXLineState;
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next_TXOneCount <= TXOneCount;
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next_TXOneCount <= TXOneCount;
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|
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
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|
next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
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case (CurrState_prcTxB) // synopsys parallel_case full_case
|
case (CurrState_prcTxB) // synopsys parallel_case full_case
|
`START_PTBY:
|
`START_PTBY:
|
begin
|
begin
|
next_processTxByteRdy <= 1'b0;
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next_processTxByteRdy <= 1'b0;
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next_USBWireData <= 2'b00;
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next_USBWireData <= 2'b00;
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| Line 142... |
Line 154... |
next_i <= 4'h0;
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next_i <= 4'h0;
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next_TxByte <= 8'h00;
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next_TxByte <= 8'h00;
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next_TxByteCtrl <= 8'h00;
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next_TxByteCtrl <= 8'h00;
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next_TXLineState <= 2'b0;
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next_TXLineState <= 2'b0;
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next_TXOneCount <= 4'h0;
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next_TXOneCount <= 4'h0;
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next_USBWireFullSpeedRate <= 1'b0;
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|
next_TxByteFullSpeedRate <= 1'b0;
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NextState_prcTxB <= `PTBY_WAIT_EN;
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NextState_prcTxB <= `PTBY_WAIT_EN;
|
end
|
end
|
`PTBY_WAIT_EN:
|
`PTBY_WAIT_EN:
|
begin
|
begin
|
next_processTxByteRdy <= 1'b1;
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next_processTxByteRdy <= 1'b1;
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| Line 153... |
Line 167... |
begin
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begin
|
NextState_prcTxB <= `PTBY_WAIT_GNT;
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NextState_prcTxB <= `PTBY_WAIT_GNT;
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next_processTxByteRdy <= 1'b0;
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next_processTxByteRdy <= 1'b0;
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next_TxByte <= TxByteIn;
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next_TxByte <= TxByteIn;
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next_TxByteCtrl <= TxByteCtrlIn;
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next_TxByteCtrl <= TxByteCtrlIn;
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next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
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next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
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next_TXOneCount <= 4'h0;
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next_TXOneCount <= 4'h0;
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next_TXLineState <= JBit;
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next_TXLineState <= JBit;
|
next_USBWireReq <= 1'b1;
|
next_USBWireReq <= 1'b1;
|
end
|
end
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else if (processTxByteWEn == 1'b1)
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else if (processTxByteWEn == 1'b1)
|
begin
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begin
|
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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next_processTxByteRdy <= 1'b0;
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next_processTxByteRdy <= 1'b0;
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next_TxByte <= TxByteIn;
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next_TxByte <= TxByteIn;
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next_TxByteCtrl <= TxByteCtrlIn;
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next_TxByteCtrl <= TxByteCtrlIn;
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next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
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next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
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next_i <= 4'h0;
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next_i <= 4'h0;
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end
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end
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end
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end
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`PTBY_WAIT_GNT:
|
`PTBY_WAIT_GNT:
|
begin
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begin
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| Line 175... |
Line 193... |
NextState_prcTxB <= `WAIT_RDY_WIRE;
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NextState_prcTxB <= `WAIT_RDY_WIRE;
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end
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end
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end
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end
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`WAIT_RDY_WIRE:
|
`WAIT_RDY_WIRE:
|
begin
|
begin
|
if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))
|
if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_IDLE1;
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NextState_prcTxB <= `LS_START_SND_IDLE1;
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end
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end
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else if (USBWireRdy == 1'b1)
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else if (USBWireRdy == 1'b1)
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begin
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begin
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| Line 275... |
Line 293... |
end
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end
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end
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end
|
`STOP_SND_SE0_2:
|
`STOP_SND_SE0_2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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if (USBWireRdy == 1'b1)
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NextState_prcTxB <= `STOP_W_RDY2;
|
begin
|
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NextState_prcTxB <= `STOP_SND_J;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= `SE0;
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next_USBWireCtrl <= `DRIVE;
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|
end
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end
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end
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`STOP_SND_SE0_1:
|
`STOP_SND_SE0_1:
|
begin
|
begin
|
if (USBWireRdy == 1'b1)
|
NextState_prcTxB <= `STOP_W_RDY1;
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begin
|
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NextState_prcTxB <= `STOP_SND_SE0_2;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= `SE0;
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next_USBWireCtrl <= `DRIVE;
|
|
end
|
|
end
|
end
|
`STOP_CHK:
|
`STOP_CHK:
|
begin
|
begin
|
if (TxByteCtrl == `DATA_STOP)
|
if (TxByteCtrl == `DATA_STOP)
|
begin
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begin
|
| Line 307... |
Line 313... |
end
|
end
|
end
|
end
|
`STOP_SND_J:
|
`STOP_SND_J:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `STOP_W_RDY3;
|
|
end
|
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`STOP_SND_IDLE:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
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NextState_prcTxB <= `STOP_W_RDY4;
|
|
end
|
|
`STOP_FIN:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
next_USBWireReq <= 1'b0;
|
|
//release the wire
|
|
NextState_prcTxB <= `PTBY_WAIT_EN;
|
|
end
|
|
`STOP_W_RDY1:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_prcTxB <= `STOP_SND_SE0_2;
|
|
next_USBWireWEn <= 1'b1;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
end
|
|
end
|
|
`STOP_W_RDY2:
|
|
begin
|
|
if (USBWireRdy == 1'b1)
|
|
begin
|
|
NextState_prcTxB <= `STOP_SND_J;
|
|
next_USBWireWEn <= 1'b1;
|
|
next_USBWireData <= `SE0;
|
|
next_USBWireCtrl <= `DRIVE;
|
|
end
|
|
end
|
|
`STOP_W_RDY3:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `STOP_SND_IDLE;
|
NextState_prcTxB <= `STOP_SND_IDLE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
end
|
end
|
end
|
`STOP_SND_IDLE:
|
`STOP_W_RDY4:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `STOP_FIN;
|
NextState_prcTxB <= `STOP_FIN;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
end
|
`STOP_FIN:
|
`LS_START_SND_IDLE3:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
next_USBWireReq <= 1'b0;
|
NextState_prcTxB <= `LS_START_W_RDY2;
|
//release the wire
|
|
NextState_prcTxB <= `PTBY_WAIT_EN;
|
|
end
|
end
|
`LS_START_SND_IDLE3:
|
`LS_START_SND_J1:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
|
NextState_prcTxB <= `LS_START_W_RDY3;
|
|
end
|
|
`LS_START_SND_IDLE1:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_J1;
|
NextState_prcTxB <= `LS_START_SND_IDLE2;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
end
|
`LS_START_SND_J1:
|
`LS_START_SND_IDLE2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
|
NextState_prcTxB <= `LS_START_W_RDY1;
|
|
end
|
|
`LS_START_FIN:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
|
|
next_i <= 4'h0;
|
|
end
|
|
`LS_START_W_RDY1:
|
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_FIN;
|
NextState_prcTxB <= `LS_START_SND_IDLE3;
|
//Drive the first JBit
|
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
end
|
`LS_START_SND_IDLE1:
|
`LS_START_W_RDY2:
|
begin
|
begin
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_IDLE2;
|
NextState_prcTxB <= `LS_START_SND_J1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
end
|
`LS_START_SND_IDLE2:
|
`LS_START_W_RDY3:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_IDLE3;
|
NextState_prcTxB <= `LS_START_FIN;
|
|
//Drive the first JBit
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
|
end
|
end
|
`LS_START_FIN:
|
|
begin
|
|
next_USBWireWEn <= 1'b0;
|
|
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
|
|
next_i <= 4'h0;
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
| Line 405... |
Line 451... |
processTxByteRdy <= 1'b0;
|
processTxByteRdy <= 1'b0;
|
USBWireData <= 2'b00;
|
USBWireData <= 2'b00;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireCtrl <= `TRI_STATE;
|
USBWireReq <= 1'b0;
|
USBWireReq <= 1'b0;
|
USBWireWEn <= 1'b0;
|
USBWireWEn <= 1'b0;
|
|
USBWireFullSpeedRate <= 1'b0;
|
i <= 4'h0;
|
i <= 4'h0;
|
TxByte <= 8'h00;
|
TxByte <= 8'h00;
|
TxByteCtrl <= 8'h00;
|
TxByteCtrl <= 8'h00;
|
TXLineState <= 2'b0;
|
TXLineState <= 2'b0;
|
TXOneCount <= 4'h0;
|
TXOneCount <= 4'h0;
|
|
TxByteFullSpeedRate <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
processTxByteRdy <= next_processTxByteRdy;
|
processTxByteRdy <= next_processTxByteRdy;
|
USBWireData <= next_USBWireData;
|
USBWireData <= next_USBWireData;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireCtrl <= next_USBWireCtrl;
|
USBWireReq <= next_USBWireReq;
|
USBWireReq <= next_USBWireReq;
|
USBWireWEn <= next_USBWireWEn;
|
USBWireWEn <= next_USBWireWEn;
|
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
i <= next_i;
|
i <= next_i;
|
TxByte <= next_TxByte;
|
TxByte <= next_TxByte;
|
TxByteCtrl <= next_TxByteCtrl;
|
TxByteCtrl <= next_TxByteCtrl;
|
TXLineState <= next_TXLineState;
|
TXLineState <= next_TXLineState;
|
TXOneCount <= next_TXOneCount;
|
TXOneCount <= next_TXOneCount;
|
|
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
